Jory I believe you probably ment to say 5X the Nyquist Rate, which is 5 x 1/2 the bit rate of 5 Gbps, or 12.5 GHz, rather than 25 GHz as you said. It is not "a" particular stub, but rather the pairing of multiple stubs and discontinuities that can cause resonance induced additional jitter. PCIe allocates most of the jitter into the Tx and Rx silicon, leaving very little for the interconnect, so it does make sense to model and simulate any "non-standard" channels. regards, Scott Jory McKinley wrote: > Jory McKinley > McKinley Consulting > e-mail: jory_mckinley@xxxxxxxxx > phone: (774)-285-2859 > > > > > > Hello Bert, > Your rough calculations are about right but remember its not the bit rate but > the edge rate we are concerned with (and subsequent frequency content) of the > PCIE signals which at 30ps (close to 20Ghz meaningful energy content) minimum > edge rates give cause of concern for these via transitions. > If we did not have the edge rate information available then we could assume > that frequencies up to about 5 times the bit rate would be a concern which in > this case would be roughly 25GHz. > Regards, > -Jory > > > > > > > ________________________________ > From: Lambert Simonovich <bertsimonovich@xxxxxxxxxx> > To: Istvan Novak <istvan.novak@xxxxxxx>; Girish Gopi > <girish.gopi@xxxxxxxxxxxxxxxxxx> > Cc: si-list@xxxxxxxxxxxxx > Sent: Sunday, July 12, 2009 8:16:29 PM > Subject: [SI-LIST] Re: PCIe routing > > Girish, > > Further from Istvan's assumption of the board being sequentially laminated > and from your overall board thickness of 3mm (0.118"), then I assume each > dielectric thickness in the stackup is approximately 0.005" and 1oz copper > layers. You mention the PCIe signals are routed on layers 2 and layer 19. > This means there is a stub from layer 2 to layer 10 and layer 19 to layer 11 > of approximately 0.055". > > We can estimate the 1/4 wave resonant frequency notch in the frequency > domain (SDD21) by the following equation; > > f = C/(4*sqrt(er)*stub_length) > > Where: > > f is 1/4 wave resonant freq > C is speed of light (1.18E10 inches/sec) > er is effective dielectric constant > sub_length is stub length in inches > > Therefore assuming an effective dielectric constant of 4.3, and stub length > of 0.055", then the 1/4 wave resonant frequency will be approx 26GHz. > > At 5GB/s, we are concerned for losses at 2.5GHz. Depending on the total > length of your channel chip to chip, and if you are traversing through a > backplane, you may have other issues unless you model the whole channel. If > on the other hand you are just going a short distance from chip to chip on > the same board, and controlling other impedance discontinuities and Xtalk, > then the effect of just the 0.055" stub(s) will be negligible at 2.5GHz. > > Regards, > > Lambert (Bert) Simonovich > President > LAMSIM Enterprises Inc. > http://lamsimenterprises.com/index.html > > > > > > -----Original Message----- > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On > Behalf Of Istvan Novak > Sent: July-12-09 9:30 AM > To: Girish Gopi > Cc: si-list@xxxxxxxxxxxxx > Subject: [SI-LIST] Re: PCIe routing > > Girish, > > >From your description it looks to me that you deal with a board with > sequential lamination, and two sub-composite pieces, maybe layer 1-10 and > layers 11-20 are built first before gluing them together. In any event, the > fact that your blind vias penetrate several layers will result in a > stub-notch frequency less than what you would expect just based on the > time-of-flight along the length of the via in the same dielectric. If you > want to squeeze the most out of your design, a 3D field solver simulations > looks necessary. > > Regards, > > Istvan Novak > SUN Microsystems > > > > > Jory McKinley wrote: > >> Hello Grish, >> Well lets see, the electrical length of the blind via you described is >> > roughly 10ps. For PCIe gen 2 the minimum rise/fall time is 30ps so these > vias could create impedance mismatches for your channel. I would try and > match as close as possible to your trace impedance with sufficient ground > via returns. If you are able try and model these vias in the channel with a > 3D simulator. > >> Regards, >> -Jory >> >> >> >> >> >> ________________________________ >> From: Girish Gopi <girish.gopi@xxxxxxxxxxxxxxxxxx> >> To: si-list@xxxxxxxxxxxxx >> Sent: Saturday, July 11, 2009 7:32:10 AM >> Subject: [SI-LIST] PCIe routing >> >> Hi all, >> I am having the 20 layer pcb with 3MM thickness , using blind vias from 1 >> > to 10 and 11 to 20 layers.Where 2nd layer using for PCIe(5GB/S) routing , > can I know that the via used for PCIe routing from layer 2 to 10 , will it > be act as a stub ?Is there any issues? > >> Thanks in advance >> Girish >> **************** CAUTION - Disclaimer *****************This email may >> contain confidential and privileged material for the sole use of the >> > intended recipient(s). Any review, use, retention, distribution or > disclosure by others is strictly prohibited. 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