[SI-LIST] Re: Reg.High-Speed LVDS interface

  • From: Steven Kan <steven@xxxxxxxxxxxxxxxxxxxx>
  • To: SI-List <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 15 Jul 2009 12:25:33 -0700

> Date: Tue, 14 Jul 2009 10:46:11 +0530
> Subject: [SI-LIST] Reg.High-Speed LVDS interface
> From: chundi srikanth <chundis@xxxxxxxxx>
> 
> Can anybody help me out in LVDS interface concerns while interfacing it with
> High-End FPGA.
> 
> We have a ADC which we are operating at 125MSPS and with serial LVDS output
> which is interfaced to Vertex-5 FPGA. The ADC is in one board and the FPGA
> will be in another board. I have to route these LVDS interface signals from
> one board to another through board to board connectivity. So what are the
> concerns i need to look up while doing this interface? Can u pls give me
> some idea on this. Will it be a problem if i run these signals with that
> speed.

Srikanth,

What is the distance from board to board? Is that 125 MSPS the parallel
data rate or the serialized data rate?

If it's reasonably short (a foot or shorter) and 125 Mbps serial rate,
you can probably just use a twisted pair cable. If the Virtex receiver
pins have programmable termination, just make sure it's set up for a 100
or 124 Ohm floating differential load.

If you need to run this for longer distances and/or at higher data
rates, then I would suggest rebuffering the outputs using a line driver.
Not surprisingly, we sell such line drivers:

http://www.pulseresearchlab.com/products/fanout/prl-424LV/424LVmain.htm

This will toggle over 1.25 GHz, and it has a 100 Ohm floating input
termination and back-terminated differential outputs. This may be
overkill for your application, but it does have some nice features, such
as 1:4 fanout so you can drive your FPGA and also have another identical
data stream for running to a scope, logic analyzer, second FPGA board, etc.
-- 
Steven Kan                                (p) 310-515-5330 x24
Pulse Research Lab                        (f) 310-515-0068
1234 Francisco St., Torrance, CA  90502   (c) 818-620-3062
mailto:steven@xxxxxxxxxxxxxxxxxxxx
http://www.pulseresearchlab.com
Signal Buffering & Translation for Digital Design, Integration & Test


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