Hi, I think the source of the confusion is the hystorical difference between RF and digital circuits. People with RF and microwave experience, and digital designers who heard about RF design techniques, claim that: 90 degree corners - create impedance discontinuities - generate EMI radiation (if the trace is on the surface) People doing digital designs in practice say that in dense high-speed digital design - impedance discontinuity of 90 degree bends does not matter - have not seen systematic measured evidence that sharp corners are an EMI problem Who is right with these seemingly contradictory statements? The funny truth is that both sets of statements are correct (please watch the wording of the above statements very closely). Here is why: It is true that 90-degree corners (and also 45-degree corners for that matter) create impedance discontinuities and create standing waves with portion of the standing wave leaking out, creating EMI radiation. However, typical traditional RF and microwave circuits have (and obviously there are always exceptions) - wide and short traces, therefore resistive trace loss is minimal - matched silicons, where not only the real part of the impedance is set properly, but also the silicon's input capacitance is tuned out - no or just the absolute minimal number of vertical via connections For the above reasons (minimal resistive trace loss, minimal or no via capacitance, minimal or no device capacitance), on traditional RF and microwave circuits, the single biggest discontinuity contributor may come from corners and (T) junctions. The equivalent capacitance of a 90-degree corner can be measured in femtoFarads. Typical via capacitance is a fraction of a pF, and (packaged silicon) device capacitance can be up to several pF. If we take out the via and device capacitances, the discontinuities created by right-angle bends become visible and show up as the biggest problem to fight. On today's dense digital boards, on the other hand, we do have vias and through holes (if not for any other reason, just for testability), which are typically several times higher in equivalent capacitance. We also have silicons, which even if they are 'matched', the imaginary part of input impedance (the input capacitance) most of the time is still not tuned out. Packaged device input capacitances are usually two orders of magnitudes higher than the capacitance of a bend. We also tend to use (because we have to) narrow, resistive traces. For these reasons, in a typical digital circuit, the impedance discontinuity of a right-angle bend does not matter (though it is present), because it is masked out by the one and two-order of magnitude bigger via and device discontinuities. Similar arguments apply to the EMI radiation: the typical 'clean' and 'flat' geometry of a RF or microwave circuit leave any sharp corner on the surface 'electrically visible', so its radiation can be measured and is not masked out by bigger factors. But on dense digital circuits, we have many right angle bends, even if not in the PCB itself: we have thousands of right-angle corners where our package pins or balls connect to the PCB, also every pin of a gull-wing package has the right-angle bend. Plus many silicon devices are not packaged in EMI-tight case, and the high-current loops on the package and on the silicon do radiate. The radiation from PCB bends, though present, is being masked out by the other, bigger and/or more numerous radiation components. As digital designs become higher speed, and we are using more point-to-point connections, with the lowest possible via count, time may come when right-angle bends in digital designs will matter more. Sharp right-angle bends on narrow traces increase the risk of opening at the inner corners during the etching process, though this should not (and does not) happen with proper manufacturing processes. This manufacturing risk can be safely eliminated altogether by using 45-degree corners. Regards Istvan Novak SUN Microsystems ----- Original Message ----- From: <ray_waugh@xxxxxxxxxxx> To: <si-list@xxxxxxxxxxxxx> Sent: Friday, August 09, 2002 9:52 AM Subject: [SI-LIST] Re: PCB tracks > > Changes in characteristic impedance do not matter as long as the mismatched section is shorter than a tenth wavelength at the highest operating frequency, and as long as it is offset by a second mismatch. For example, a short section of narrow line (high impedance) can be nicely offset by a short section of wide line (low impedance), forming a low pass filter with a cutoff frequency higher than your highest operating frequency. > > Radiation in TEM mode microstrip lines is a function of frequency, board thickness and board dielectric constant. Thin boards and boards with a high dielectric constant restrict the E-fields of the line (keep them close to the ground plane) and inhibit radiation. 32 mil FR4 works very nicely to 6 or 8 GHz, and 16 mil FR4 would not radiate anything you can measure at 15 GHz. > > Ray > > Raymond Waugh > Agilent Technologies > ray_waugh@xxxxxxxxxxx > > -----Original Message----- > From: Ismail B - CTD, Chennai. [mailto:ismailb@xxxxxxxxxxxxxxx] > Sent: Friday, August 09, 2002 3:09 AM > To: gurunath.kulkarni@xxxxxxxxx; cadpro2k@xxxxxxxxxx; SI-LIST > Subject: [SI-LIST] Re: PCB tracks > > > > Hi GVK, > > I think there will be a sudden change in charateristic impedance at 90 deg > bends due to increase in trace width at those points. This change in > impedance will set up reflections on the trace. As far as EMI is concerned I > have a feeling that pointed edges do radiate more that curved edges. > However, Im not sure about other members comments (Perhaps, I have not > experimented on this ). Generally, We prefer 45 deg bends on our boards. > > Regards, > Ismail > > > -----Original Message----- > From: gurunath vinayakrao kulkarni [mailto:gurunath.kulkarni@xxxxxxxxx] > Sent: Friday, August 09, 2002 3:18 PM > To: cadpro2k@xxxxxxxxxx; SI-LIST > Subject: [SI-LIST] Re: PCB tracks > > > Hi Mitch, > > I meant 45 deg and not 90 deg. If you have 90 deg , there will problems when > the current flows through the trace, the steep edge ( 90 deg) will act as > antenna and there will some EMI problems( emit radiations). When the > electrons hit the edge , there will sudden change in the direction of the > flow of the current, so this creates the emission effects. Please anybody > correct me if I am wrong. > > GVK > ----- Original Message ----- > From: <cadpro2k@xxxxxxxxxx> > To: "SI-LIST" <si-list@xxxxxxxxxxxxx> > Sent: Thursday, August 08, 2002 11:00 PM > Subject: [SI-LIST] Re: PCB tracks > > > > Hi GVK, > > > > I think you misspoke. I'm sure you meant to say "usually 90 deg is OK" > > CAD tools make it so easy to do the 45s, and we, the PCB designers, have > > been asked to make them all 45 for the longest time, since the > > engineering community drove the CAD tool vendors for the 45 degree > > option. Still, so much time is wasted day in and day out on "cleansing" > > the board ("NO! I can't have 90 degree bends on my board with a clock > > speed of 100Mhz!"), and making all the buried layers look appealing. I > > still contend the 45 degree theory is a fallacy, and I think it's been > > proven time and again (see http://www.ultracad.com , notes section). > > > > Ranting over. > > > > Mitch > > > > ---------Included Message---------- > > > Date: Thu, 8 Aug 2002 17:45:38 +0530 > > > From: "gurunath vinayakrao kulkarni" > > > I agree with Philippe Robert as I have not seen the PCB with > > curved traces > > > usually 45 deg is O.K > > > > > > GVK > > _____________________________________________________________ > > > > > > ------------------------------------------------------------------ > > To unsubscribe from si-list: > > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > > > > or to administer your membership from a web page, go to: > > //www.freelists.org/webpage/si-list > > > > For help: > > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > > > > List archives are viewable at: > > //www.freelists.org/archives/si-list > > or at our remote archives: > > http://groups.yahoo.com/group/si-list/messages > > Old (prior to June 6, 2001) list archives are viewable at: > > http://www.qsl.net/wb6tpu > > > > > > > > -- Attached file included as plaintext by Ecartis -- > -- File: Wipro_Disclaimer.txt > > **************************Disclaimer************************************ > > Information contained in this E-MAIL being proprietary to Wipro Limited is > 'privileged' and 'confidential' and intended for use only by the individual > or entity to which it is addressed. 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