[SI-LIST] Re: PCB Warpage during Assembly
- From: steve weir <weirsi@xxxxxxxxxx>
- To: leeritchey@xxxxxxxxxxxxx,"RakeshBit" <rakesh@xxxxxxxxxxxxx>, "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 22 May 2006 09:02:31 -0700
Lee, those are the metric equivalent of 1oz/sq ft.
Regards,
Steve.
At 08:12 AM 5/22/2006, Lee Ritchey wrote:
>Rakesh,
>
>If I understand it, you have 3 ounce copper in most of your layers. Why
>so thick? That is way too much copper for any logic board we are likely to
>design. (I use 1/2 ounce copper layers for both planes and signal layers
>for a 3 terabit routers all consuming on the order of 7 KW and power
>distribution worked just fine with reasonable IR drop in the pwoer layers.)
>
>If, in fact, you have such thick copper, I'd start by reducing the
>thickness in all layers to 1/2 ounce. That will help both warpage and
>cost.
>
>Copper balance or fill is not necessarily going to stop the warping. I
>build stackups with this kind of imbalance all the time without warping.
>
>In my experience, warping is caused by materials (laminate weave) that
>shrinks excessively when is is strain relieved due to the heat of
>soldering. This is traceable to the initial materials used by your
>fabricator. Some laminate is preshrunk, just like the cloth in a pair of
>levis, and some is not. The really good fabricators know this and only use
>preshrunk materials. The low bidders, as a rule, do not. My guess is your
>PCBs are being built by the low bidder.
>
>I'd reduce the copper thickness and find a more capable fabricator.
>
>
> > [Original Message]
> > From: RakeshBit <rakesh@xxxxxxxxxxxxx>
> > To: si-list <si-list@xxxxxxxxxxxxx>
> > Date: 5/22/2006 9:11:26 AM
> > Subject: [SI-LIST] PCB Warpage during Assembly
> >
> > Hi,
> > We have designed a PCI based board which has 4-Spartan3 FPGAs. ( FF1152
> > package - plastic pack)
> >
> > The PCB size is 210 mm by 170 mm
> >
> > The layer stack is as follows.
> >
> > 0.0325 Copper palting layer 1 5.5 mil trace width, 50 ohms single ended
> > 0.0175 Copper foil layer 1
> > 0.0940 Prepreg 1 - 2
> > 0.0350 Copper foil layer 2 plane
> > 0.1524 Core 2 - 3
> > 0.0350 Copper foil layer 3 5 mil trace width, 50 ohms single ended
> > 0.1778 Prepreg 3 - 4
> > 0.0350 Copper foil layer 4 plane
> > 0.1016 Core 4 - 5
> > 0.0350 Copper foil layer 5 4.4 mil trace width, 50 ohms single ended
> > 0.0940 Prepreg 5 - 6
> > 0.0350 Copper foil layer 6 4.4 mil trace width, 50 ohms single ended
> > 0.1016 Core 6 - 7
> > 0.0350 Copper foil layer 7 plane
> > 0.1016 Prepreg 7 - 8
> > 0.0350 Copper foil layer 8 4.5 mil trace width, 50 ohms single ended
> > 0.0762 Core 8 - 9
> > 0.0350 Copper foil layer 9 4.5 mil trace width, 50 ohms single ended
> > 0.1016 Prepreg 9 - 10
> > 0.0350 Copper foil layer 10 plane
> > 0.0762 Core 10 - 11
> > 0.0350 Copper foil layer 11 plane
> > 0.0940 Prepreg 11 - 12
> > 0.0175 Copper foil layer 12
> > 0.0325 Copper plating layer 12 5.5 mil trace width, 50 ohms single ended
> > 1.6209 Total PCB thickness in mm
> >
> >
> > The problem we are facing is that there is excessive warping of the PCB
> > during assembly.
> > we tried chaning the stack, and are now contemplating copper balance /
> > copper fill on all layer.?
> >
> > Could any one please throw light on what could be the problem, as we have
> > taken 3-trials and all have failed.
> >
> > Please guide.
> >
> > with warm regards
> > Rakesh Mehta
> >
> >
> >
> >
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