[SI-LIST] Re: PCB Warpage during Assembly
- From: "Nima Lotfi" <lnima@xxxxxxxxxx>
- To: <rakesh@xxxxxxxxxxxxx>, "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 23 May 2006 13:16:23 -0400
Rakesh,
Your board is lacking symmetry. For example Core 2-3 is 6 mils, and
Core 10-11 is 3 MIL. (I've take the liberty of converting to MILS).
There are few prepregs layers that are lacking symmetry.
Note that you need to have symmetrical plans as well. That is if you
have plane on layer 3 you need to have a plane on layer 10, etc.
I think fixing them might resolve your problem, but this might mean a
complete re-layout.
mm mils=09
0.0325 1.28 Copper palting layer 1 5.5 mil trace width, 50
ohms single ended
1 0.0175 0.69 Copper foil layer 1
0.094 3.7 Prepreg 1 - 2
2 0.035 1.38 Copper foil layer 2 plane
0.1524 6 Core 2 - 3
3 0.035 1.38 Copper foil layer 3 5 mil trace width, 50 ohms
single ended
0.1778 7 Prepreg 3 - 4
4 0.035 1.38 Copper foil layer 4 plane
0.1016 4 Core 4 - 5
5 0.035 1.38 Copper foil layer 5 4.4 mil trace width, 50 ohms
single ended
0.094 3.7 Prepreg 5 - 6
6 0.035 1.38 Copper foil layer 6 4.4 mil trace width, 50 ohms
single ended
0.1016 4 Core 6 - 7
7 0.035 1.38 Copper foil layer 7 plane
0.1016 4 Prepreg 7 - 8
8 0.035 1.38 Copper foil layer 8 4.5 mil trace width, 50 ohms
single ended
0.0762 3 Core 8 - 9
9 0.035 1.38 Copper foil layer 9 4.5 mil trace width, 50 ohms
single ended
0.1016 4 Prepreg 9 - 10
10 0.035 1.38 Copper foil layer 10 plane
0.0762 3 Core 10 - 11
11 0.035 1.38 Copper foil layer 11 plane
0.094 3.7 Prepreg 11 - 12
12 0.0175 0.69 Copper foil layer 12
0.0325 1.28 Copper plating layer 12 5.5 mil trace width, 50
ohms single ended
Thanks,=20
______________________=20
Nima Lotfi, P. Eng=20
Digital Hardware Design Engineer=20
Nortel
758-7786 ESN=20
(403) 769-7786 Direct=20
(403) 769-5350 Fax=20
LNima@xxxxxxxxxxxxxxxxxx=20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of RakeshBit
> Sent: Sunday, May 21, 2006 11:49 PM
> To: si-list
> Subject: [SI-LIST] PCB Warpage during Assembly
> Importance: High
>=20
> Hi,
> We have designed a PCI based board which has 4-Spartan3 FPGAs. (
FF1152
> package - plastic pack)
>=20
> The PCB size is 210 mm by 170 mm
>=20
> The layer stack is as follows.
>=20
> 0.0325 Copper palting layer 1 5.5 mil trace width, 50 ohms single
ended
> 0.0175 Copper foil layer 1
> 0.0940 Prepreg 1 - 2
> 0.0350 Copper foil layer 2 plane
> 0.1524 Core 2 - 3
> 0.0350 Copper foil layer 3 5 mil trace width, 50 ohms single ended
> 0.1778 Prepreg 3 - 4
> 0.0350 Copper foil layer 4 plane
> 0.1016 Core 4 - 5
> 0.0350 Copper foil layer 5 4.4 mil trace width, 50 ohms single ended
> 0.0940 Prepreg 5 - 6
> 0.0350 Copper foil layer 6 4.4 mil trace width, 50 ohms single ended
> 0.1016 Core 6 - 7
> 0.0350 Copper foil layer 7 plane
> 0.1016 Prepreg 7 - 8
> 0.0350 Copper foil layer 8 4.5 mil trace width, 50 ohms single ended
> 0.0762 Core 8 - 9
> 0.0350 Copper foil layer 9 4.5 mil trace width, 50 ohms single ended
> 0.1016 Prepreg 9 - 10
> 0.0350 Copper foil layer 10 plane
> 0.0762 Core 10 - 11
> 0.0350 Copper foil layer 11 plane
> 0.0940 Prepreg 11 - 12
> 0.0175 Copper foil layer 12
> 0.0325 Copper plating layer 12 5.5 mil trace width, 50 ohms single
ended
> 1.6209 Total PCB thickness in mm
>=20
>=20
> The problem we are facing is that there is excessive warping of the
PCB
> during assembly.
> we tried chaning the stack, and are now contemplating copper balance /
> copper fill on all layer.?
>=20
> Could any one please throw light on what could be the problem, as we
have
> taken 3-trials and all have failed.
>=20
> Please guide.
>=20
> with warm regards
> Rakesh Mehta
>=20
>=20
>=20
>=20
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