[SI-LIST] Re: PCB Warpage during Assembly
- From: steve weir <weirsi@xxxxxxxxxx>
- To: rakesh@xxxxxxxxxxxxx,"si-list" <si-list@xxxxxxxxxxxxx>
- Date: Sun, 21 May 2006 23:48:35 -0700
Asymmetric stack-ups are prone to warping problems. Balance your stack-up.
Steve.
At 10:48 PM 5/21/2006, RakeshBit wrote:
>Hi,
>We have designed a PCI based board which has 4-Spartan3 FPGAs. ( FF1152
>package - plastic pack)
>
>The PCB size is 210 mm by 170 mm
>
>The layer stack is as follows.
>
> 0.0325 Copper palting layer 1 5.5 mil trace width, 50 ohms
> single ended
> 0.0175 Copper foil layer 1
> 0.0940 Prepreg 1 - 2
> 0.0350 Copper foil layer 2 plane
> 0.1524 Core 2 - 3
> 0.0350 Copper foil layer 3 5 mil trace width, 50 ohms single ended
> 0.1778 Prepreg 3 - 4
> 0.0350 Copper foil layer 4 plane
> 0.1016 Core 4 - 5
> 0.0350 Copper foil layer 5 4.4 mil trace width, 50 ohms single ended
> 0.0940 Prepreg 5 - 6
> 0.0350 Copper foil layer 6 4.4 mil trace width, 50 ohms single ended
> 0.1016 Core 6 - 7
> 0.0350 Copper foil layer 7 plane
> 0.1016 Prepreg 7 - 8
> 0.0350 Copper foil layer 8 4.5 mil trace width, 50 ohms single ended
> 0.0762 Core 8 - 9
> 0.0350 Copper foil layer 9 4.5 mil trace width, 50 ohms single ended
> 0.1016 Prepreg 9 - 10
> 0.0350 Copper foil layer 10 plane
> 0.0762 Core 10 - 11
> 0.0350 Copper foil layer 11 plane
> 0.0940 Prepreg 11 - 12
> 0.0175 Copper foil layer 12
> 0.0325 Copper plating layer 12 5.5 mil trace width, 50 ohms
> single ended
>1.6209 Total PCB thickness in mm
>
>
>The problem we are facing is that there is excessive warping of the PCB
>during assembly.
>we tried chaning the stack, and are now contemplating copper balance /
>copper fill on all layer.?
>
>Could any one please throw light on what could be the problem, as we have
>taken 3-trials and all have failed.
>
>Please guide.
>
>with warm regards
>Rakesh Mehta
>
>
>
>
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