[SI-LIST] Re: Mysterious "glitch" in the simulation?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 26 Jul 2011 16:52:26 -0700
Cuong, if your signal quality at the die is deficient, then you need to
go figure out why. If it is sufficient, then you are done. If you are
worried about other signals, evaluate those signals where it matters:
at the die.
Steve.
On 7/26/2011 4:25 PM, Cuong Nguyen wrote:
> Hi Dan,
>
> Thanks for the suggestion. It's unfortunate that I could not post the
> screenshots to clarify my
> Points. The circuit is very simple: One driver, series resistor, T-line,
> and receiver. The
> "glitch" is a small one (not multiple like a reflection) that is crossing
> the threshold area.
>
> If one choose to probe at the die and disregard signaling at the pins, then
> aren't we ignoring
> potential crosstalks and EMI issues to adjacent signals? Other word, I
> can't just say
> "Oh life is good at the die and I'm gonna forget the rest of the board?"
>
> Thoughts?
>
> Cuong
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of Dan Smith
> Sent: Tuesday, July 26, 2011 3:58 PM
> To: Cuong Nguyen; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Mysterious "glitch" in the simulation?
>
> Cuong,
>
> One observation I have seen multiple times is there is a glitch if
> simulating at the pin vs. the die. (you eluded in your email that the
> glitch goes away if you choose the die). Just like any transmission line,
> if you do not probe at the end (e.g., at the pin and not the die), you have
> reflections returning to the point of probe from the final destination (the
> die). Remember, who cares what the pin sees it is what the decision circuit
> sees (in this case the die) that matters.
>
> Dan
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of Cuong Nguyen
> Sent: Tuesday, July 26, 2011 3:49 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Mysterious "glitch" in the simulation?
>
> Content-Type: text/plain;
> charset="us-ascii"
> Content-Transfer-Encoding: 7bit
> Colleagues,
>
>
>
> I'm seeing a small "glitch" in a relatively simple simulation and would like
> to solicit your expert observations.
>
> Instead of showing 2 circuits and 2 scope traces I'm showing one set only
> but will try to explain.
>
>
>
> 1. The original circuit does NOT have the series R1 resistor (17-ohm
> suggested by the wizard)
>
> 2. The scope trace shows the result of the original circuit.
>
>
>
> My observations:
>
>
>
> 1. The "glitch" stays in both cases (with or without the series
> termination)
>
> 2. With termination, the upper value of the voltage output is reduced
> and the lower value
>
> is increased a little. The general shapes are the same in both cases.
> However, because
>
> the "glitch" is shifted down (with termination) this now crosses the
> threshold area and becomes
>
> problematic.
>
>
>
> The questions are:
>
>
>
> 1. What is this glitch? Is it from the package model? (If I choose
> die I do not see the glitch)
>
> 2. What might be some ways to resolve this? (Or, is this some
> simulation artifact?)
>
>
>
> Thanks for your inputs
>
>
>
>
>
>
>
>
>
>
>
>
>
> === === === === === ===
>
> Cuong Nguyen
>
> Field Application Engineer
>
> EDA Direct Inc
>
>
>
>
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--
Steve Weir
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