[SI-LIST] Re: Mysterious "glitch" in the simulation?

  • From: "Beal, Weston" <Weston_Beal@xxxxxxxxxx>
  • To: "Nguyen, Cuong - EDA Direct" <cuong@xxxxxxxxxxxxx>, 'steve weir' <weirsi@xxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 26 Jul 2011 23:52:47 +0000

Cuong,

The glitch is a reflection from the die. The IBIS model includes a pin model 
that the simulator represents with a transmission line. Therefore, the 
measurement point at the pin is between to transmission line segments. The 
impedance of the buffer at the die is most certainly not the same as the 
impedance of the transmission line representing the package. There are 
termination techniques that can remove the glitch, but each method has an 
associated cost. As others have stated, you probably don't need to worry about 
this small reflection.

Weston


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Nguyen, Cuong - EDA Direct
Sent: Tuesday, July 26, 2011 4:38 PM
To: 'steve weir'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Mysterious "glitch" in the simulation?

Scope photo:

http://imageshack.us/photo/my-images/34/tmp1n.jpg/

Circuit topology:

http://imageshack.us/photo/my-images/197/tmp22n.jpg/

Measurements were made at the receiver end at the pin.  Measurements at the die 
(not shown) do not show the glitch.

Cuong

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of steve weir
Sent: Tuesday, July 26, 2011 4:13 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Mysterious "glitch" in the simulation?

The SI-LIST server strips attachments.  Post your pictures to something like 
imageshack and include a link.

What is the topology from the driver to the receiver?  Where are you measuring 
in your simulation?

A double inflection such as a glitch implies L/C or Tx line reflection.  
That the series termination does not seem to affect the glitch much implies 
that the oscillation occurs between the driver and the transmission line.  
Excessive package inductance and/or capacitance for the driver's edge rate and 
strength could do such things to you.



Steve.
On 7/26/2011 3:48 PM, Cuong Nguyen wrote:
> Content-Type: text/plain;
>       charset="us-ascii"
> Content-Transfer-Encoding: 7bit
> Colleagues,
>
>
>
> I'm seeing a small "glitch" in a relatively simple simulation and 
> would
like
> to solicit your expert observations.
>
> Instead of showing 2 circuits and 2 scope traces I'm showing one set 
> only but will try to explain.
>
>
>
> 1.       The original circuit does NOT have the series R1 resistor (17-ohm
> suggested by the wizard)
>
> 2.       The scope trace shows the result of the original circuit.
>
>
>
> My observations:
>
>
>
> 1.       The "glitch" stays in both cases (with or without the series
> termination)
>
> 2.       With termination, the upper value of the voltage output is
reduced
> and the lower value
>
> is increased a little.  The general shapes are the same in both cases.
> However, because
>
> the "glitch" is shifted down (with termination) this now crosses the 
> threshold area and becomes
>
> problematic.
>
>
>
> The questions are:
>
>
>
> 1.       What is this glitch?  Is it from the package model?  (If I choose
> die I do not see the glitch)
>
> 2.       What might be some ways to resolve this?  (Or, is this some
> simulation artifact?)
>
>
>
> Thanks for your inputs
>
>
>
>
>
>
>
>
>
>
>
>
>
> === === === === === ===
>
> Cuong Nguyen
>
> Field Application Engineer
>
> EDA Direct Inc
>
>
>
>
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--
Steve Weir
IPBLOX, LLC
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Reno, NV  89501
www.ipblox.com

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