[SI-LIST] Re: Memory CAS Latency (CL2 vs CL3)
- From: "Michael Greim" <mgreim@xxxxxxxx>
- To: <erdinih@xxxxxxxxx>, <kenny_frohlich@xxxxxxxxx>
- Date: Thu, 23 Aug 2007 07:20:51 -0500
http://en.wikipedia.org/wiki/CAS_latency
Best Regards,
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Michael C. Greim
Cray Platform Engineering
512-740-9097
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And all this science they don't understand
is just my job six days a week.....
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We will either find a way
or make one...... -Hannibal
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of Ihsan Erdin
Sent: Thursday, August 23, 2007 6:17 AM
To: kenny_frohlich@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Memory CAS Latency (CL2 vs CL3)
Kenny,
CL# is basically the number of the clock edges that follow the /CAS
signal assertion in order to latch in the data signal. If that
duration falls short of the column access time the device will not
register the data. Using a CL2 programming for a CL3 device may cause
such a problem.
Regards
Ihsan
On 8/23/07, Kenny Frohlich <kenny_frohlich@xxxxxxxxx> wrote:
> When CAS latency is said to be CL2, does it mean CAS# line will assert =
for 2 clock cycles?. Likewise, CAS# line will assert for 3 clock cycles =
if CL3?
>
> Thanks you,
> Kenny
>
>
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