[SI-LIST] regarding the stack up
- From: Govinda samy <samynitt@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 23 Aug 2007 06:00:14 -0700 (PDT)
I am planning to have 8 layer stack up on my board . The following is the
structure
--------- top
--------- GND
Signal
PWR-1
PWR -2
Signal
----------- GND
---------- Bottom
PWR - 1 and PWR-2 is spilit plane with multiple voltages . 1.2V , 3.3V, 5 V,
2.5 V
All the DDR related voltages also included in that PWR-2 plane : 1.25V, 2.5V
My question is, this Layer stack up is acceptable ? Because my concern is the
high speed switching and transient current doesn't have any GND path
underneath..
is that will create any noise or ripples on the power rails ???
Please let me know your point of views ..
Looking for a deal? Find great prices on flights and hotels with Yahoo!
FareChase.
____________________________________________________________________________________
Pinpoint customers who are looking for what you sell.
http://searchmarketing.yahoo.com/
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
