[SI-LIST] regarding the stack up

  • From: Govinda samy <samynitt@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 23 Aug 2007 06:00:14 -0700 (PDT)

I am planning to have 8 layer stack up on my  board . The following is the 
--------- top
--------- GND
PWR -2
----------- GND
---------- Bottom
PWR - 1 and PWR-2 is spilit plane with multiple voltages . 1.2V , 3.3V, 5 V, 
2.5 V
All the DDR related  voltages also included in that PWR-2 plane : 1.25V, 2.5V
My question is,  this Layer stack up is acceptable ? Because my concern is the 
high speed switching and transient current doesn't have any GND path 
is that will create any noise or ripples on the power rails ??? 
Please let me know your point of views ..

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