[SI-LIST] Re: Memory CAS Latency (CL2 vs CL3)

  • From: "Ihsan Erdin" <erdinih@xxxxxxxxx>
  • To: kenny_frohlich@xxxxxxxxx
  • Date: Thu, 23 Aug 2007 07:17:06 -0400

Kenny,

CL# is basically the number of the clock edges that follow the /CAS
signal assertion in order to latch in the data signal. If that
duration falls short of the column access time the device will not
register the data. Using a CL2 programming for a CL3 device may cause
such a problem.

Regards

Ihsan

On 8/23/07, Kenny Frohlich <kenny_frohlich@xxxxxxxxx> wrote:
> When CAS latency is said to be CL2, does it mean CAS# line will assert for 2 
> clock cycles?.  Likewise, CAS# line will assert for 3 clock cycles if CL3?
>
>   Thanks you,
>   Kenny
>
>
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