[SI-LIST] Re: Matching impedance
- From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
- To: silist <si-list@xxxxxxxxxxxxx>
- Date: Mon, 3 Feb 2003 14:39:48 -0800
Betty,
While I don't know what kind of circuits you are working on, my experiences
on I/O's @ 3-10GHz that have to run over a reasonable distant on a system do
not have a single impedance over all frequencies. Depending on whether the
driver implements pre-emphasis or FIR type filter, they can have 2,3 or even
up to 5 "states" of impedances depending on the pattern. At 10GHz, the
topology (package, trace, parasitic) can have 40-60db per decade
attenuation. I think it is meaningless to view the termination scheme
without slapping on the multi-state driver with topology and go through the
simulation analysis and empirically find out which termination value
generates the best eye-opening.
One thing good about running signal at such a high speed is all the ringing
tend to die down quickly along the signal path. Think about it this way, if
you have such a hard time sending the signal at its fundamental frequency,
the ringing (which has to be higher than the fundamental) will suffer even
more attenuation.
Chris
ps are you related to Prof. Frank Luk ?
-----Original Message-----
From: Betty Luk [mailto:bl87@xxxxxxxxxxx]
Sent: Monday, February 03, 2003 1:53 PM
To: arpad.muranyi@xxxxxxxxx; silist
Subject: [SI-LIST] Re: Matching impedance
Arpad,
Some clarification on #2.
Essentially the problem that I'm trying to solve is that I have a signal
generator (with 50ohms internally) which has to drive a CMOS chip (my
DUT). So I'm trying to design a test board with 50ohm lines which will
operate hopefully, up to 3-10GHz (I would like to test the DUT using
multiple frequencies). Since on one end of this packaging I have 50ohms,
and the other almost an open circuit, some impedance matching or
termination is necessary to reduce the reflections (resistor is placed on
the board outside of the chip package).
So referring to Johnson and Graham's book, it would seem that parallel
termination with resistors may be appropriate. However, over what
frequency range would this be valid? In the discussion of parallel
termination with resistors, the termination resistor = 50ohms for a 50ohm
transmission line. This does not seem to take into account the DUT (bond
wire inductance, parasitic capacitance and resistance). It would seem that
if taking into account the parasitics of the DUT, a 50ohm parallel resistor
would not match the 50ohm of the transmission line. Thus, is this parallel
resistor termination scheme only valid if the parasitics of the DUT are
such that they can be ignored?
Thanks.
Betty.
At 01:25 PM 2/3/2003 -0800, Muranyi, Arpad wrote:
>Betty,
>
>Here are my answers:
>
>1) I have to separate the question into two parts. If you are
>talking about analysis, the answer can be yes and no. You can
>still perform small signal AC (or frequency domain) analysis on
>interconnects which will have those types of signals on them to
>figure out whether your design has problems or not, but those
>results will not necessarily reveal what happens when the bus
>stops and starts. You just have to know what the results mean.
>If you are talking about building a trace that is terminated
>with a tuned 1/4 wave stub, or something like that, you will
>probably not be successful. Ask yourself the question, 1/4
>wave of what frequency?
>
>2) I feel this question has some terminology or conceptual
>problem built into it. What is the termination in your mind?
>The resistor alone? You didn't mention where that resistor is.
>It could be outside the package (I assume that is your case),
>but it could also be on the die (the place where it really
>should be to terminate the stub of the package). If you have
>an external termination resistor, and you do not include the
>package and input capacitance of your receiver, you will not=20
>see their effects in your simulations (which are actually
>connected in parallel with your "termination" resistor.
>Depending on the proportions of your parasitics and signal
>frequencies this may or may not be negligible. You decide.
>
>3) Whether to use discrete RLC for the package or not, depends
>again on the proportions. Some packages are long relatively to
>the signal frequencies. They should be modeled as transmission
>lines. If you have slower signals they may be modeled with
>lumped elements, again, you decide.
>
>In general, if you go fast enough, the signal path ends at the
>fist transistor on the die. Everything is a T-line to that point,
>consequently a stub, depending on your topology. When you start
>slowing things down, you can simplify your models by ignoring or
>lumping certain parts of your circuit.
>
>I hope I gave some answers to your questions, even if I wasn't
>talking black and white. But that's why it is called "Black Magic"
>and not "Black and White Magic" ... :-)
>
>Arpad
>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
=
>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
=
>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
>
>
>-----Original Message-----
>From: Betty Luk [mailto:bl87@xxxxxxxxxxx]
>Sent: Monday, February 03, 2003 12:37 PM
>To: silist
>Subject: [SI-LIST] Re: Matching impedance
>
>
>
>Arpad,
>
>Thanks for your response. A couple of questions:
>
>1) so are you saying that RF techniques are usually not as applicable =
>for=20
>data or address signals?
>
>2) i am trying to match a 50ohm line which drives CMOS gates. This is =
>the=20
>driving signal for the transmitter that I am testing (i.e. it is a data=20
>signal). So if i choose to use resistive termination, would i be, in =
>fact,=20
>ignoring the parasitic capacitance, resistance of the chip input as well =
>as=20
>the bond wire inductance?
>
>3) and if i want to take into account these parasitics, would i then =
>move=20
>to a termination scheme involving discrete RLC elements?
>
>Thanks again.
>Betty.
>
>At 12:17 PM 2/3/2003 -0800, Muranyi, Arpad wrote:
>
> >Betty,
> >
> >What people forget, or forget to mention often is that RF
> >techniques usually use steady state analysis, i.e. your
> >signals have to be ever lasting, or continuously running.
> >This may be true for clocks (but not even those are always
> >continually running) but it is definitely not true for data
> >or address signals.
> >
> >The latter two types of signals can switch anywhere from 0 Hz to
> >the maximum operating frequency of the design. This translates
> >into step response vs. steady state sinusoidal analysis, and
> >can make a big difference in your answers.
> >
> >Arpad Muranyi
> >Intel Corporation
>
>=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
>3D=3D3D=3D3D=3D3D
> >
> >
> >
> >-----Original Message-----
> >From: Betty Luk [mailto:bl87@xxxxxxxxxxx]
> >Sent: Monday, February 03, 2003 12:08 PM
> >To: scott@xxxxxxxxxxxxx; whizplayer@xxxxxxxxx
> >Cc: silist
> >Subject: [SI-LIST] Re: Matching impedance
> >
> >
> >
> >Hello,
> >
> >I am a bit confused as to when certain impedance matching schemes =
>should =3D
> >be=3D20
> >used. (This is related to the question I posted last week =
>regarding=3D20
> >impedance matching for high freq PCB). There seems to be two major =3D
> >categories
> >
> >1) resistive termination (this seems to be the accepted method for most =
>=3D
> >PCBs)
> >2) as referenced below, Microwave techniques (such as stub =
>matching,=3D20
> >tapered lines, etc)
> >
> >Which method should be used when?
> >
> >Thanks in advance,
> >Betty
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