[SI-LIST] Re: Long T reflection problems
- From: "McKinley, Jory D" <jory.d.mckinley@xxxxxxxxx>
- To: <james.stein@xxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 2 Mar 2005 12:54:47 -0500
Hello James,
Based on the information you provided you should expect a reflection
from the O/C in "normal" operation. To dampen these reflections the
series resistor at the T-Junction will do the job however you may
degrade the signal level to the receiving buffer and you will still be
left with some ringing at the O/C end and possibly at the junction. I
would setup a simulation to determine the acceptable receiver signal
levels and ringing. In general and you can work backwards from this for
T-Junctions if you use series resistor(s) that are approximately 1/3 the
50ohm t-line then you can roughly expect the signal degrading by 1/2
through the T-Junction with no reflections at the junction.
-Jory
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Stein, James F (UK)
Sent: Wednesday, March 02, 2005 11:14 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Long T reflection problems
Hi All,
Here is some more information (the PCB is being designed at the moment
so I=3D
can state
the intentions but don't have a definitive answer).
The signals being talked about are 5V TTL but there will be 3.3V =
LVTTL=3D
signals with a similar
situation on the pcb as well.
The tracks will be approx 50-55 Ohm.
The logic analyser probe access will be through a test connector
breakout=3D
pcb with 2.54 pitch headers. The breakout pcb will have tracks with
the=3D
same impedance as the main pcb, and trace length should be no more
than=3D
50mm. The analyser will probably be an HP one with an HP adapter on
the=3D
end of the analyser ribbon cable for 20 way 2.54 pitch headers (I know
the=3D
HP adapter which is an off the shelf part has some sort of termination
in=3D
it but not sure what at the moment).
My plans for termination at the moment was to put a low value series=3D
resistor on the trace just as it splits away from the T junction
between=3D
the two transceivers towards the test connector, say 39R. However i'm
not=3D
convinced it will be sufficient for when the trace is left o/c and =
for=3D
when it's connected to the analyser so i'm really leaving it open to=3D
advice before I get any simulation done.
Regards
James
James,
You did not really give a very complete description of the trace
topology so no one will be able to tell you what you will see. You
didn't give voltage signaling level, if the traces are routed on 50 Ohm
traces, what logic analyzer probes you are using, how you plan to
terminate... The sort answer is: you will certainly get ringing due to
reflection, but we don't know what you can tolerate as far as timing and
or voltage ringing.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Stein, James F (UK)
Sent: Wednesday, March 02, 2005 8:00 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Long T reflection problems
Hi Everyone,
I have question about signal reflections, I have added some specific
data=3D3D but rule of thumb answers are all welcome as i'm new to SI!
I have a bi-directional signal that is loaded with an LV-CMOS
transceiver=3D3D at 5pF on each end and a dt_r/dt/f of approx.
0.3 to 0.5 ns. The frequency of data across this is about 2 MHz. =
The=3D3D
distance between the two buffers is about 15mm.=3D3D0D This signal needs
to
be observed externally with a logic analyser for test=3D3D
purposes.=3D3D0D=3D
The
track between the two transceivers is t'd to a test connector giving
a=3D3D
t'd track length of about 150mm.=3D3D0D In normal operation the analyser
would not be connected so the long track=3D3D section is o/c; when
connected to an analyser then you could probably add a metre to the
total track length.
In this case, what sort of SI problems would I expect to see, both with
the=3D3D track o/c and also plugged into an analyser?
Would series termination be sufficient to prevent reflections, or
should=3D3D the test signal go through a buffer (last resort really)
before
the test connector?
Regards
James
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