[SI-LIST] Re: Long T reflection problems
- From: "gsletch" <gsletch@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 03 Mar 2005 00:24:31 -0000
As long as the stub length(time delay)is less than 1/2 of 0.3ns, it
can be modeled as a lumped capacitive load with or without the
analyzer connected. A reflection at a capacitive lumped load looks
like a small voltage bump in your signal. Of course, you would want
the stub to be placed exactly in the center of the main trace and
choose a stub track width that would equal out to 5 pf...same as the
other load...equal loads, equally spaced...make sure the loaded
impedance of the line and stub are the same.
You could choose either series termination or parallel termination,
but make that resistor value equate to the loaded impedance of the
line.
Of course, if the length cannot be less than 1/2 0.3ns, the stub would
look like a another transmission line and the problem becomes more
difficult with modeling reflections at long stubs, etc.
This is my preliminary stab at your problem, anyway...hope that
helps...
--- In si-list@xxxxxxxxxxxxxxx, "Stein, James F (UK)"
<james.stein@xxxx> wrote:
>
> Hi Everyone,
>
> I have question about signal reflections, I have added some specific
data=
> but rule of thumb answers are all welcome as
> i'm new to SI!
> I have a bi-directional signal that is loaded with an LV-CMOS
transceiver=
> at 5pF on each end and a dt_r/dt/f of approx.
> 0.3 to 0.5 ns. The frequency of data across this is about 2 MHz.
The=
> distance between the two buffers is about 15mm.=0D
> This signal needs to be observed externally with a logic analyser
for test=
> purposes.=0D
> The track between the two transceivers is t'd to a test connector
giving a=
> t'd track length of about 150mm.=0D
> In normal operation the analyser would not be connected so the long
track=
> section is o/c; when connected to an
> analyser then you could probably add a metre to the total track
length.
>
> In this case, what sort of SI problems would I expect to see, both
with the=
> track o/c and also plugged into an analyser?
> Would series termination be sufficient to prevent reflections, or
should=
> the test signal go through a buffer (last resort really) before
> the test connector?
>
>
> Regards
>
> James
>
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