[SI-LIST] Re: Length matching of source synchronous busses.
- From: "Jeremy Plunkett" <jeremy@xxxxxxxxxxxxxxx>
- To: scott@xxxxxxxxxxxxx, andrew.m.volk@xxxxxxxxx
- Date: Fri, 7 Mar 2003 20:18:20 -0800
Scott,
The logic of a 10mil matching requirement is that the difference in =
routing expense (design time, board area) between length-matching to a =
200mil spec and length matching to a 10mil spec is minor and well worth =
the extra 33ps of timing margin in some cases. This is an especially =
low-hanging fruit when only a few signals are involved, such as =
differential clocks.
There is no implication that the system will not work without this level =
of matching; layout guidelines are meant to illustrate "best design =
practice", not necessarily to give the absolute limits on how crummy any =
particular aspect of the system can be. It is always possible to make =
tradeoffs in particular cases, however the layout engineer has to keep =
in mind that the majority of systems will be designed and validated =
following the layout guidelines, so departures from the guidelines take =
on extra risk.
regards,
Jeremy
|>--/\/\/--((((((((()--|>
Jeremy Plunkett
Signal Integrity Engineer
ServerWorks Corp
www.serverworks.com
|>--/\/\/--((((((((()--|>
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Scott McMorrow
Sent: Friday, March 07, 2003 4:30 PM
To: andrew.m.volk@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Length matching of source synchronous busses.
Andrew,
I've replied to you in detail off the list. If you feel it appropriate, =
you can forward my comments to the list and see what others think. =20
Over the years, I've thought about these matters quite a bit. However,=20
when a design guideline states that traces in a bus must be matched to=20
within +/- 10 mils, with correction for internal package trace lengths,=20
there are several tacit assumptions that the designer that uses your=20
guidelines makes:
1) That the bus will not work without this level of extreme matching.
2) That the bus will work with this level of extreme matching.
3) That all other sources of timing margin degradation have been fully=20
accounted for.
Without additional supporting timing and noise margin analysis, you=20
force the conclusion that you have no significant margin, statistical=20
or otherwise, in the complete system design. To me, this has always=20
seemed to be a bad way to design systems and opens them up to unforseen=20
failure mechanisms.
scott
--=20
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
Volk, Andrew M wrote:
>Scott -
>
>Gosh, you just listed a lot of good reasons for controlling what we =
can. =3D
> New multi-hundred megahertz buses don't have a lot of margin. It is =
=3D
>much easier to spec length matching than explicit via shapes, etc. The =
=3D
>tools seem to support this type of board analysis quite well. The real =
=3D
>question for me is what is the cost of matching? At what level of =3D
>matching is it prohibitively costly? I would take the position that I =
=3D
>would spend extra time to match the layout, etc., to give me system =3D
>margin, than to deal with marginal systems.
>
>Regards,
>Andrew Volk
>Intel Corp.
>
>
>-----Original Message-----
>From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
>Sent: Friday, March 07, 2003 12:47 PM
>To: steven.corey@xxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Controlled Impedance Coupon Design
>
>
>Steve,
>
><snip>
>-------------- segue into complaint section =
----------------------------
>
>As a segue into a related topic, I shake my head when =
semiconductor=3D20
>vendors provide bus design guidelines that require trace matching =
within =3D
>
>+/- 10 mils on an FR4 substrate. (Yes, I did see this specification =
in=3D20
>a recent design guideline.) This is equivalent to saying that delay =
must =3D
>
>be matched to within 1.8 ps (give or take a few friendly =
femtoseconds.)=3D20
> I can spit on a microstrip trace and see much greater delay than =
that.=3D20
>Variations in via pad and antipad dimensions, along with =
registration,=3D20
>will cause greater delay than that. And must I mention that with =
woven=3D20
>materials (like FR4) routing directionality will cause greater =
delay=3D20
>than that. Oh, and has anyone looked at the routing in the =
packages=3D20
>these guys are using. A package plating tail will introduce delays =
that =3D
>
>vary with frequency and neighbor tail coupling.
>
>What are they thinking?
>-------------- end of complaint section =
--------------------------------
>
>
>best regards,
>
>scott
>
>
> =20
>
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