[SI-LIST] Re: Length matching of source synchronous busses.
- From: "Jerry Martinson" <jmartinson@xxxxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 10 Mar 2003 18:39:11 -0800
While reading this thread, I was reminded of an issue I had seen about
two years ago that goes along the same line of needing to take
everything into account when trying to length or delay match nets. When
matching rules are as close as 0.010", many non-obvious effects are
often more significant than the residual length difference.
Layer-dependent effects can have a surprisingly large impact on flight
time depending on the layer you are on and the mode of transmission.
I'm sure many of the readers of this thread had probably thought of this
and have taken this into account when trying to 'delay' match but some
of the subtleties aren't always obvious (at least it wasn't to me at the
time) so I thought I'd mention it so someone doesn't mess up like I
almost did.
I once worked on some very high-density FR4 boards. The fabricator came
up with some surprising numbers for impedance that didn't match the
geometric specifications for the traces. What should have been 35 ohms
at 1GHz (found by inputting the geometries and Dk into one of those
web-based IPC impedance calculators) was turning out to be 50 ohms
according to the fabricator. When I inquired further about the
discrepancy (I thought they were just accounting for the real traces
being thinner and more trapezoidal than the nominal rectangles as well
as Dk variability) I found out that my layers had become so thin that
the glass/epoxy ratios deviated significantly from the 45/55 mix because
of 1-ply construction. Obviously you can only have an integer number of
glass layers.
Furthermore, since the material is inhomogeneous, what really matters is
the field strength through particular portions of the material.
Obviously, this can vary wildly from layer to layer and depending on
what other tracks nearby are doing (i.e. single ended vs differential).
This greatly affects both impedance and flight time.
Prior to realizing this (and it retrospect it is shocking that I didn't
think of it earlier), I had planned to skew a differential clock line to
account for some extra hold time needed at a receiver on the
single-ended data lines. I had very naively assumed that the delay per
inch was the same as they were on the same layer or a layer with similar
Dk. After analyzing it at a greater level of detail, I found that I
needed to do the exact opposite - I was ~500 pS off!
A problem I faced when doing this was that a lot of the details about
fabricating dense boards are not freely available to plug into a
field-solver so it seems that you have to rely on the fabricators'
numbers. The particular fabricator I worked with didn't even use a
field solver but rather used empirical data derived from similar boards
as they felt that empirical data better captured and predicted the real
results compared to any model that they plugged into a field solver. =20
-Jerry
-----Original Message-----
From: Ken Cantrell [mailto:Ken.Cantrell@xxxxxxxxxxx]=20
Sent: Monday, March 10, 2003 8:16 AM
To: scott@xxxxxxxxxxxxx; Jeremy Plunkett; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Length matching of source synchronous busses.
All,
I concur with Scott. I found the P1(package length) vs L1(breakout
segment)particularly interesting. P1 is 750 mils +/- 500 mils (which as
Scott pointed out, the end user doesn't currently have access to that
data),
and L1 max is 500 mils. The error tolerance on P1 is equal to the L1
maximum length. That's a little confusing for me, and got a good laugh
when
I discussed it with our layout group. I can't repeat the response to
the 10
mil clock matching length.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Scott McMorrow
Sent: Saturday, March 08, 2003 10:43 AM
To: Jeremy Plunkett; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Length matching of source synchronous busses.
Jeremy,
In the case I was referring to, 10 mil matching was required on the
signals within each group of a QDR and DDR memory bus. That matching
requirement included length corrections for the individual package trace
lengths. In fact, the company that provided the specification (which
seems to have been copied from another group within the company) did not
and cannot provide the trace lengths of the package at this time, which
makes the rule worthless.
As a slight side note, even when manufacturers provide on package
trace length guidelines, they usually fail to specify what the Er or
propagation delay of the on package interconnect is, making matching
correction on the external PCB an improbable exercise.
My point is that design guidelines which are written without good,
exact, accurate supporting analysis information on all sources of timing
and noise error (and I have yet to see one that does) fail to give OEM
designers and layout professionals the information necessary to
understand the implications of meeting or failing to meet trace length
matching requirements. Yes, I understand that this is low hanging
fruit, however it is low hanging fruit without the necessary supporting
documentation.
OEM designers are not equiped to analyze the on die and on package
issues, as semiconductor companies are lothe to provide the necessary
information, such as package layouts, material properties, bump
locations and redistribution layer modeling. Since much of the
crosstalk on a non perfectly terminated bus is reflected reverse
crosstalk, it turns out that in many conventional busses most of the
coupling and jitter has been developed on die and within the package.
Designers tend to overdesign the PCB interconnect, since accurate
modeling of the internal interconnect is not possible.
So, with trace length matching to 10 mils, you may decrease the delay
skew in one area of the interconnect (although you may increase the
total skew if the internal package interconnect has not been accounted
for correctly), when compared to a 200 mil matching requirement.
However, I would not advocate this anyway. I would advocate better
design, timing and noise documentation which allows designers to make
their own informed conclusions as to the amount of trace matching
required in their design. Until the semiconductor companies provide
this (and I apologize to any company that does and I am unaware of)
their trace matching rules are at best a "hedge" against "things that go
bump in the night," that they do not fully understand, or have not fully
characteracterized, or want to hide from designers.
best regards,
scott
Jeremy Plunkett wrote:
>Scott,
>The logic of a 10mil matching requirement is that the difference in
routing
expense (design time, board area) between length-matching to a 200mil
spec
and length matching to a 10mil spec is minor and well worth the extra
33ps
of timing margin in some cases. This is an especially low-hanging fruit
when only a few signals are involved, such as differential clocks.
>
>There is no implication that the system will not work without this
level of
matching; layout guidelines are meant to illustrate "best design
practice",
not necessarily to give the absolute limits on how crummy any particular
aspect of the system can be. It is always possible to make tradeoffs in
particular cases, however the layout engineer has to keep in mind that
the
majority of systems will be designed and validated following the layout
guidelines, so departures from the guidelines take on extra risk.
>
>regards,
>Jeremy
>
>
>|>--/\/\/--((((((((()--|>
>
>Jeremy Plunkett
>Signal Integrity Engineer
>ServerWorks Corp
>www.serverworks.com
>
>|>--/\/\/--((((((((()--|>
>
>
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Scott McMorrow
>Sent: Friday, March 07, 2003 4:30 PM
>To: andrew.m.volk@xxxxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Length matching of source synchronous busses.
>
>
>
>Andrew,
>
>I've replied to you in detail off the list. If you feel it
appropriate,
>you can forward my comments to the list and see what others think.
>
>Over the years, I've thought about these matters quite a bit. However,
>when a design guideline states that traces in a bus must be matched to
>within +/- 10 mils, with correction for internal package trace lengths,
>there are several tacit assumptions that the designer that uses your
>guidelines makes:
>
>1) That the bus will not work without this level of extreme matching.
>
>2) That the bus will work with this level of extreme matching.
>
>3) That all other sources of timing margin degradation have been fully
>accounted for.
>
>Without additional supporting timing and noise margin analysis, you
>force the conclusion that you have no significant margin, statistical
>or otherwise, in the complete system design. To me, this has always
>seemed to be a bad way to design systems and opens them up to unforseen
>failure mechanisms.
>
>scott
>
>
>
--
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
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