[SI-LIST] Length matching of source synchronous busses.
- From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
- To: andrew.m.volk@xxxxxxxxx
- Date: Fri, 07 Mar 2003 16:29:49 -0800
Andrew,
I've replied to you in detail off the list. If you feel it appropriate,
you can forward my comments to the list and see what others think.
Over the years, I've thought about these matters quite a bit. However,
when a design guideline states that traces in a bus must be matched to
within +/- 10 mils, with correction for internal package trace lengths,
there are several tacit assumptions that the designer that uses your
guidelines makes:
1) That the bus will not work without this level of extreme matching.
2) That the bus will work with this level of extreme matching.
3) That all other sources of timing margin degradation have been fully
accounted for.
Without additional supporting timing and noise margin analysis, you
force the conclusion that you have no significant margin, statistical
or otherwise, in the complete system design. To me, this has always
seemed to be a bad way to design systems and opens them up to unforseen
failure mechanisms.
scott
--
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
Volk, Andrew M wrote:
>Scott -
>
>Gosh, you just listed a lot of good reasons for controlling what we can. =
> New multi-hundred megahertz buses don't have a lot of margin. It is =
>much easier to spec length matching than explicit via shapes, etc. The =
>tools seem to support this type of board analysis quite well. The real =
>question for me is what is the cost of matching? At what level of =
>matching is it prohibitively costly? I would take the position that I =
>would spend extra time to match the layout, etc., to give me system =
>margin, than to deal with marginal systems.
>
>Regards,
>Andrew Volk
>Intel Corp.
>
>
>-----Original Message-----
>From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
>Sent: Friday, March 07, 2003 12:47 PM
>To: steven.corey@xxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Controlled Impedance Coupon Design
>
>
>Steve,
>
><snip>
>-------------- segue into complaint section ----------------------------
>
>As a segue into a related topic, I shake my head when semiconductor=20
>vendors provide bus design guidelines that require trace matching within =
>
>+/- 10 mils on an FR4 substrate. (Yes, I did see this specification in=20
>a recent design guideline.) This is equivalent to saying that delay must =
>
>be matched to within 1.8 ps (give or take a few friendly femtoseconds.)=20
> I can spit on a microstrip trace and see much greater delay than that.=20
>Variations in via pad and antipad dimensions, along with registration,=20
>will cause greater delay than that. And must I mention that with woven=20
>materials (like FR4) routing directionality will cause greater delay=20
>than that. Oh, and has anyone looked at the routing in the packages=20
>these guys are using. A package plating tail will introduce delays that =
>
>vary with frequency and neighbor tail coupling.
>
>What are they thinking?
>-------------- end of complaint section --------------------------------
>
>
>best regards,
>
>scott
>
>
>
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
