[SI-LIST] Re: Length matching of source synchronous busses.
- From: "Jeremy Plunkett" <jeremy@xxxxxxxxxxxxxxx>
- To: scott@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Tue, 11 Mar 2003 01:54:44 -0800
Scott,
It may be that our in-house layout engineers are exceptionally talented =
(or possibly exceptionally pliable), but I have yet to have any heavy =
objects thrown at me for requiring a 25mil matching spec within a =
source-synchronous group. And I can testify that they work under the =
same degree of time pressure as our customer's layout people (if not =
greater).
Here's my perspective: the person setting the length matching spec tries =
to find the "knee of the curve" where the additional gain in timing =
margin from tightening the matching spec is no longer worth the =
additional time required from the layout engineer. In discussions with =
the aforementioned talented/pliable layout guys we have in-house, we =
concluded that once you are going through the process of adding =
serpentines on pretty much every signal in a bus(which is required for =
package length compensation in any case), setting the length of the =
serpentines to match the total length within 25mils is only slightly =
more time-consuming that adjusting them to match within 100mils. In =
fact, in our experience getting them to match within 5 mil is only =
slightly harder that 25 mils (and some of our customers choose to do =
this); the reason we don't ask for it is that there isn't much of a =
point, since as you and others have noted there are plenty of other =
sources of delay variation in the board that are not reflected in the =
length extraction such as the pad connections, fiberglass weave =
directions, temperature gradients, resistor placement, etc etc. =20
If customers found this requirement to be especially irksome, I would =
expect to receive some significant pushback on the subject, but that has =
not been the case. =20
In situations where a matching requirement (or any part of our topology =
recommendations) is making it difficult to route a bus, we do receive =
feedback from our own layout engineers as well as customers and we are =
very careful to take all factors into account in making the tradeoff.
regards,
Jeremy
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Scott McMorrow
Sent: Saturday, March 08, 2003 9:43 AM
To: Jeremy Plunkett; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Length matching of source synchronous busses.
Jeremy,
In the case I was referring to, 10 mil matching was required on the=20
signals within each group of a QDR and DDR memory bus. That matching=20
requirement included length corrections for the individual package trace =
lengths. In fact, the company that provided the specification (which=20
seems to have been copied from another group within the company) did not =
and cannot provide the trace lengths of the package at this time, which=20
makes the rule worthless. =20
As a slight side note, even when manufacturers provide on package
trace length guidelines, they usually fail to specify what the Er or
propagation delay of the on package interconnect is, making matching
correction on the external PCB an improbable exercise.
My point is that design guidelines which are written without good,=20
exact, accurate supporting analysis information on all sources of timing =
and noise error (and I have yet to see one that does) fail to give OEM=20
designers and layout professionals the information necessary to=20
understand the implications of meeting or failing to meet trace length=20
matching requirements. Yes, I understand that this is low hanging=20
fruit, however it is low hanging fruit without the necessary supporting=20
documentation.
OEM designers are not equiped to analyze the on die and on package=20
issues, as semiconductor companies are lothe to provide the necessary=20
information, such as package layouts, material properties, bump=20
locations and redistribution layer modeling. Since much of the=20
crosstalk on a non perfectly terminated bus is reflected reverse=20
crosstalk, it turns out that in many conventional busses most of the=20
coupling and jitter has been developed on die and within the package.=20
Designers tend to overdesign the PCB interconnect, since accurate=20
modeling of the internal interconnect is not possible.
So, with trace length matching to 10 mils, you may decrease the delay=20
skew in one area of the interconnect (although you may increase the=20
total skew if the internal package interconnect has not been accounted=20
for correctly), when compared to a 200 mil matching requirement.=20
However, I would not advocate this anyway. I would advocate better=20
design, timing and noise documentation which allows designers to make=20
their own informed conclusions as to the amount of trace matching=20
required in their design. Until the semiconductor companies provide=20
this (and I apologize to any company that does and I am unaware of)=20
their trace matching rules are at best a "hedge" against "things that go =
bump in the night," that they do not fully understand, or have not fully =
characteracterized, or want to hide from designers.
best regards,
scott
Jeremy Plunkett wrote:
>Scott,
>The logic of a 10mil matching requirement is that the difference in =
routing expense (design time, board area) between length-matching to a =
200mil spec and length matching to a 10mil spec is minor and well worth =
the extra 33ps of timing margin in some cases. This is an especially =
low-hanging fruit when only a few signals are involved, such as =
differential clocks.
>
>There is no implication that the system will not work without this =
level of matching; layout guidelines are meant to illustrate "best =
design practice", not necessarily to give the absolute limits on how =
crummy any particular aspect of the system can be. It is always =
possible to make tradeoffs in particular cases, however the layout =
engineer has to keep in mind that the majority of systems will be =
designed and validated following the layout guidelines, so departures =
from the guidelines take on extra risk.
>
>regards,
>Jeremy
>
>
>|>--/\/\/--((((((((()--|>
>
>Jeremy Plunkett
>Signal Integrity Engineer
>ServerWorks Corp
>www.serverworks.com
>
>|>--/\/\/--((((((((()--|>
>
>
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Scott McMorrow
>Sent: Friday, March 07, 2003 4:30 PM
>To: andrew.m.volk@xxxxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Length matching of source synchronous busses.
>
>
>
>Andrew,
>
>I've replied to you in detail off the list. If you feel it =
appropriate,=20
>you can forward my comments to the list and see what others think. =20
>
>Over the years, I've thought about these matters quite a bit. However, =
>when a design guideline states that traces in a bus must be matched to=20
>within +/- 10 mils, with correction for internal package trace lengths, =
>there are several tacit assumptions that the designer that uses your=20
>guidelines makes:
>
>1) That the bus will not work without this level of extreme matching.
>
>2) That the bus will work with this level of extreme matching.
>
>3) That all other sources of timing margin degradation have been fully=20
>accounted for.
>
>Without additional supporting timing and noise margin analysis, you=20
>force the conclusion that you have no significant margin, statistical=20
>or otherwise, in the complete system design. To me, this has always=20
>seemed to be a bad way to design systems and opens them up to unforseen =
>failure mechanisms.
>
>scott
>
> =20
>
--=20
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at: =20
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages=20
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
=20
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
