[SI-LIST] Re: IBIS Timing Analysis
- From: "Jon Powell" <jonpowell@xxxxxxxxxxxx>
- To: <ndempshe@xxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 9 Jun 2003 08:42:02 -0700
Wow,
It looks like you have slighly overlapping ideas.
Some SI tools will automatically subtract out the part of the OUTPUT delay
associated with driving the test load. (This is called TIME_TO_VM in XTK at
least). This means that the delays sent to the Static Timing engine are
pre-compensated and the Static Timing should do nothing. It also means that
the delays can be negative, which confuses some static timing programs.
If the Static TIming tool thinks that it knows how to the compensation with
no help from the SI tool, then you should just turn off the compensation
generation in the SI tool. In some SI tools (Like XTK) this is a menu
parameter.
Being an SI guy, I would trust the SI tool compensation more (cause the
delay data is generated by simulation of the same IBIS model that is used
for the time of flight) but it really depends on how your SI and TIMING
tools want to work together and I think your final answer has to be Tool
Dependent. (So either call customer support or tell us what you are using
and see if anyone knows the specific answer).
regards,
Jon Powell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of
ndempshe@xxxxxxxxxxxxxx
Sent: Monday, June 09, 2003 8:13 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS Timing Analysis
Greetings SI List,
I have a quick question.
I am analyzing timing with our board simulation tool.
The test load indicated in the IBIS model is not the same as the load
provided in the data
sheet and for the PCI bus signals - the PCI bus specified load.
When calculating flight times, the simulator is enabled to automatically
subtract out the
test load delay so that I do not double count the IO buffer delay when
adding flight time
to the datasheet clock to Q times.
Will the difference between the IBIS model test load and the data sheet test
load make
this timing budget technique inaccurate?
If this is a problem, are there any suggestions on how best to handle this?
Should I disable the automatic delay subtracting feature of the tool to
obtain flight
times which do not subtract out the test load buffer delay. Then simulate
the IBIS model
into the test load to obtain the buffer delay into the test load. Then,
subtract this
value from the simulator flight times in a separate spreadsheet to obtain
more accurate
flight times?
OR
Should I change the test load in the IBIS model to correspond to the
datasheet or PCI
specified load?
OR ???
Your help is much needed and appreciated.
Thanks,
Ned Dempsher
L-3 Communications
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