[SI-LIST] IBIS Timing Analysis
- From: ndempshe@xxxxxxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 9 Jun 2003 11:13:12 -0400 (EDT)
Greetings SI List,
I have a quick question.
I am analyzing timing with our board simulation tool.
The test load indicated in the IBIS model is not the same as the load provided
in the data
sheet and for the PCI bus signals - the PCI bus specified load.
When calculating flight times, the simulator is enabled to automatically
subtract out the
test load delay so that I do not double count the IO buffer delay when adding
flight time
to the datasheet clock to Q times.
Will the difference between the IBIS model test load and the data sheet test
load make
this timing budget technique inaccurate?
If this is a problem, are there any suggestions on how best to handle this?
Should I disable the automatic delay subtracting feature of the tool to obtain
flight
times which do not subtract out the test load buffer delay. Then simulate the
IBIS model
into the test load to obtain the buffer delay into the test load. Then,
subtract this
value from the simulator flight times in a separate spreadsheet to obtain more
accurate
flight times?
OR
Should I change the test load in the IBIS model to correspond to the datasheet
or PCI
specified load?
OR ???
Your help is much needed and appreciated.
Thanks,
Ned Dempsher
L-3 Communications
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