[SI-LIST] Re: Hypertransport(HT) to Ethernet Bridge solutions

  • From: "Michael Khusid" <mkhusid@xxxxxxxxxx>
  • To: <harjeet.randhawa@xxxxxxxxxxxxxxxxx>
  • Date: Thu, 13 Nov 2003 12:21:33 -0500

Curiously enough, your most cost-effective solution can be a desktop
chipset. It will easily beat a price of any Hypertransport-supporting FPGA.

Check out http://www.via.com.tw/en/k8-series/k8t800.jsp



----------------------------------------------------------------
Michael Khusid
Ansoft Corporation
SI/HF Application Engineer
 
25 Burlington Mall Road, 5th floor
Burlington, MA 01803-4100
 
Tel 781-229-8900 Ext. 134 
Fax 781-229-8624
---------------------http://www.ansoft.com ---------------------

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Harjeet Singhrandhwa
Sent: Thursday, November 13, 2003 7:15 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Hypertransport(HT) to Ethernet Bridge solutions

Hi IS People,

My query is not exactly related to SI, but I am sure of some tips/leads
on this.

I am looking for s chip providing the HT to Ethernet bridging
functionality.

Any references for the same would be of great help.

Thanx in advance,
Regards,

*********************************************
Harjeet Singh Randhawa
*********************************************


-----Original Message-----
From: Jean_Pierre.Bouthemy@xxxxxxxxxx
[mailto:Jean_Pierre.Bouthemy@xxxxxxxxxx]=20
Sent: Thursday, November 13, 2003 4:08 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] QDRII clock design


Hi SI Experts,

Just a question:
Do you think that the following clock signals K/KN, C/CN (from FPGA to
QDRII) and CQ/CQN (from QDRII to FPGA) should be considered as
differential signals, with equal length in order to minimize skew, and
thus routed as differential signals with coupling (risk of crosstalk?).

Any comment will be welcome.
Thank you for your help.

Jean-Pierre.

------------------------------------------------------------------------
--
Jean-Pierre BOUTHEMY
Hardware Design Engineer
ALCATEL - Mobile Networking Division (MCG)
Mobile Core R&D
+33 (0)2 99 26 08 18
mailto:jean_pierre.bouthemy@xxxxxxxxxx



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