[SI-LIST] Hypertransport(HT) to Ethernet Bridge solutions
- From: "Harjeet Singhrandhwa" <harjeet.randhawa@xxxxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 13 Nov 2003 17:45:27 +0530
Hi IS People,
My query is not exactly related to SI, but I am sure of some tips/leads
on this.
I am looking for s chip providing the HT to Ethernet bridging
functionality.
Any references for the same would be of great help.
Thanx in advance,
Regards,
*********************************************
Harjeet Singh Randhawa
*********************************************
-----Original Message-----
From: Jean_Pierre.Bouthemy@xxxxxxxxxx
[mailto:Jean_Pierre.Bouthemy@xxxxxxxxxx]=20
Sent: Thursday, November 13, 2003 4:08 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] QDRII clock design
Hi SI Experts,
Just a question:
Do you think that the following clock signals K/KN, C/CN (from FPGA to
QDRII) and CQ/CQN (from QDRII to FPGA) should be considered as
differential signals, with equal length in order to minimize skew, and
thus routed as differential signals with coupling (risk of crosstalk?).
Any comment will be welcome.
Thank you for your help.
Jean-Pierre.
------------------------------------------------------------------------
--
Jean-Pierre BOUTHEMY
Hardware Design Engineer
ALCATEL - Mobile Networking Division (MCG)
Mobile Core R&D
+33 (0)2 99 26 08 18
mailto:jean_pierre.bouthemy@xxxxxxxxxx
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