[SI-LIST] Re: How to estimating signal waveforms at inaccessible points in DDR3 or 4?
- From: Robbie Liu <luliu@xxxxxxxxxx>
- To: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 28 Jan 2015 03:26:30 +0000
Hi Hermann:
Thank you so much for your long writing , but I think that is the
SI-list want:)
I totally agree with you that the single slot or directly mounted on
board case may be simplified on de-embedding, but the margin may not always
good even they are designed for dual slot case, for example, you may found the
controller package is 2 layer design without reference plane, and the PCB is 4
layers with bad PDN design , so you margin may eat by large SSN noise,
crosstalk , reflection and ISI ,you may have limit resource to separate these
noise/jitter, so a high precise de-embedded technology will give you confidence
on debugging such a complex system, but ,you are right, most of time , a
transmission line is enough.
one addition question is , how the receiver side input impedance (or
terminal resistance) will affect the de-embedding result? Like the different
ODT value or ODT off.
For the memory compliance setup suggestion ,I will send another message
to you , thanks again.
Thanks and Regards,
LIU Luping
-----Original Message-----
From: Hermann Ruckerbauer [mailto:Hermann.Ruckerbauer@xxxxxxxxxxxxx]
Sent: Tuesday, January 27, 2015 3:59 PM
To: Robbie Liu; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: How to estimating signal waveforms at inaccessible
points in DDR3 or 4?
Hello,
for a Point to Point connection (Single Slot, single Rank) with only writes you
will get quite reasonable results even when just embedding an ideal
transmissionline delay from your measurement point to the die (assuming you are
at least close to the memory component).
This will remove the most critical point in your measurement which is the
reflection that is causing a plateau.
So far in most of my measurements I did this and did not utilize interposers ..
but I have to admit, using such interposers would have made life simpler
several times ...
As e. g. DDR3 memory subsystems are designed to handle dual slot, dual channel
at 1600 there is often enough margin in such a P2P system that this
simplification already gives reasonable results and allow a judgement between
good and bad design.
In case you use the interposer you have at least the interposer model from your
vendor available and you can easily de-embedd the stub and the probe (at least
for the keysight solution, but I guess for other vendors as well). What is
still missing is the package model, that you can take from the IBIS. But the
closer you are at the die the simpler and more accurate will be the
de-embedding setup. So in such a configuartion this should not be the big issue
any more.
But I have to admit for my own interposer design I have still to create the
model for de-embedding .. let's see when there is real need (and
time ;-) ) to do so.
But as discussed in the past: you can spend endless time in optimizing your
setup and getting better models for embedding/de-embedding.
Overall I think the specification should adjust to reality ;-)
For DIMM based solutions maybe one can adjust to some of the serial link
standards techniques:
- e.g. define the signal quality at the connector.
- This leaves still an issue for solder down solutions .. but this is in High
speed serial links there as well and maybe interposer would solve this issue ...
- define a low level test support in the Controller/DRAM that drive out defined
data (even the system is not really powered up, a bit more than current read
calibration data Testmode).
- Define Testboards that allow simple measurments (e. g. CLB as DIMM to test a
motherboard or CBB as Motherboard to test a DIMM)
- Splitting RX/TX and Controller/DRAM measurments In the meantime I think I
have an idea how the PCIe Gen3 RX compliance is working (still trying to verify
this one) and maybe this concept would be also reasonable ..
Last but not least (maybe even most important): I think the on-Die measurements
will overtake this part before it is critical enough that it is absolutely
required to change anything.
On the controller side there are already many controllers out that can handle
this, and on the DRAM side we had already some prototypes that did this 6 years
ago when I was working at Qimonda. Especially with DDR4 Vref Adjustment
capability there is nearly everything available that is required even without
additional DRAM features ..
I think the equipment vendors will loose their grounds here ... But this might
be topic for another discussion ...
Sorry for again writing to long ..
Hermann
P.S. is anybody interested in developping such a Memory "Compliance Test" setup
? Not sure how far we will come without controller or DRAM vendor support, but
there might be some options .. e. g. for Altera contrtollers I think it should
be possible to generate a testsetup to measure CA, DQ Write and maybe even DQ
Read performance.
It would be really a nice and interesting project ..
Our next Events:
Seminar "Open the Black Box of Memory" (13-14.04.2015) in Stockholm Sweden
Embedded World 2015 (24-26.02.2015) in Nuremberg
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Itzlinger Strasse 21a
94469 Deggendorf
Tel.: +49 (0)991 / 29 69 29 05
Mobile: +49 (0)176 / 787 787 77
Fax: +49 (0)3212 / 121 9008
Am 27.01.2015 um 07:32 schrieb Robbie Liu:
> Hi Hermann:
> Thank you for your reply, yes , both the question you mentioned, the ODT
> monitor and separate the read/write , is still challenging, especially for a
> dual slot dual rank system. But we may make the thing simple first , for
> example , the 1 slot and 1 rank system, with an always write control.
>
>
> Thanks and Regards,
> LIU Luping
>
>
>
>
> -----Original Message-----
> From: Hermann Ruckerbauer [mailto:Hermann.Ruckerbauer@xxxxxxxxxxxxx]
> Sent: Saturday, January 24, 2015 1:24 AM
> To: Robbie Liu; si-list@xxxxxxxxxxxxx
> Cc: tom@xxxxxxxxxxxxxxxxx; Charles.Grasso@xxxxxxxxxxxx;
> heidi_barnes@xxxxxxxxxxxx; sherman.chen@xxxxxxx
> Subject: Re: [SI-LIST] How to estimating signal waveforms at inaccessible
> points in DDR3 or 4?
>
> Hello,
>
> In addition to getting the passive models for embedding the multipoint and
> variable termination of the DDR memory bus is causing big problems.
> So even if you have the models ot the channel your run into the issue, that
> you need to know which termination settings are applied to use tools like
> infiniisim.
> So you need exactly to know the termination scheme for e. g. writes to the
> given rank. To know this you might need to monitor ODT signals to other ranks
> and also need to know dynamic termination.
> One can build quite complex embedding structures with Infiniisim, but a
> double slot memory system will bring also such a tools to the edge what is
> possible.
> You need also to know the Memory controller TX Ron and have a model of the
> complete channel to do this correct.
>
> And last but not least the separation between Write/Read and also Write to
> the specific rank need to be decoded exactly.
>
> And your scope application might take for overshoots the complete trace and
> not only the write bursts, but for read bursts the De-Embedding setup is not
> correct.
> So even if you do have the models available it is a really tricky task to
> implement the setup for the embedding correctly.
>
> Question is how accurate you want/need to be .. often i work with the very
> simplified setup that I measure after the serial termination on the DIMM and
> just embedd the rest of the routing on the DIMM (and assume some specific
> termination scheme).
> But I know that this is only a very rough estimation of the problem ...
>
> Hermann
>
> Our next Events:
> Seminar "Open the Black Box of Memory" (13-14.04.2015) in Stockholm
> Sweden Embedded World 2015 (24-25.02.2015) in Nuremberg
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> Itzlinger Strasse 21a
> 94469 Deggendorf
> Tel.: +49 (0)991 / 29 69 29 05
> Mobile: +49 (0)176 / 787 787 77
> Fax: +49 (0)3212 / 121 9008
>
> Am 23.01.2015 um 10:06 schrieb Robbie Liu:
>> Dear All:
>>
>> You may treat this question as a follow up discussion of recently
>> hot discussion "tips of using TDR probe " and "Pin vs. Die", so I may
>> thanks to those experts first ,for their wonderful knowledge sharing.
>>
>> The question will be met by many hardware engineers such that our
>> DDR3/4 chip may be imaging mounted on board , or the board use HDI so you
>> can't have test point close enough to the end.
>>
>> Take DDR write as example, If we just have a test point (TP1)10mm
>> away from the DDR3 chip, and you want to estimate the signal waveform at
>> the DDR3 die (TP2 ), we need to know the S21 from TP1 to TP2, but for most
>> of us didn't have such capability to access the TP2, so the problem comes.
>>
>> Certainly you can use 2D or 3D EM tool to get the channel S
>> parameter, but the high accuracy need experience , and the package file is
>> difficult to get.
>>
>> So can we just use one port test from TP1 ,to get the S parameter of
>> this two port network?
>>
>>
>> We notice two papers recently mentioned this topic , one is by
>> Tomohiro Kinoshita, Shoichi Hara, Eiji Takahashi ,Panasonic, A technique for
>> estimating signal waveforms at inaccessible points in high speed digital
>> circuits, 2013 9th International Workshop on Electromagnetic Compatibility
>> of Integrated Circuits (EMC Compo), December 15-18, Nara. Japan, it use
>> their own Novel Electromagnetic Tool 'MomCACE' to get the ABCD matrix from
>> TP1 to TP2, then estimate the waveform at the channel end.
>> Another is by Evelyn Mintarno#1, Steven Ji*2 , A Practical Method to
>> Characterize Interconnect in a Fully Loaded System, and its Application to
>> DDR3 Channel, Proceedings of the 38th European Microwave Conference, , based
>> on my understand (maybe wrong ), the method is use for characterize the
>> channel between the CPU and the SO DIMM connector, right? I was wondering
>> if we can push it further , like the PCB +Package, so that we can use the s
>> parameter to estimate signal waveforms at inaccessible points in high
>> speed digital circuits, for example , the imaging mounted DDR3 chip on
>> board. The condition at port 2 may change between ODT 40, ODT 75 and
>> ODT120, or ODT OFF, not sure if it is possible.
>> What is your opinions ? do you have better solutions?
>>
>>
>>
>>
>> Thanks and Regards,
>> LIU Luping
>>
>>
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