[SI-LIST] Re: How to connect to GND planes
- From: Jim Roberts <jgroberts@xxxxxxxxxx>
- To: parnold@xxxxxxxxxxxxxxx
- Date: Wed, 30 Oct 2002 17:30:14 +0100
Peter,
Routing over a power plane is risky especially with sensitive signals
such as clocks.
I very much agree with the "stitching" i.e. vias at the edge of the
board. The corners and discontinuities in the routing launch parallel plate
modes that eminate between planes and launch as "slot" antennaes into the
environment.
I also agree that there are usually sufficient component vias, however
when it comes tro evaluation of a board there are often insuffiecient grounds
for grounding probes near strategic measuring points.
Its good to consider where you wish to measure and probe.
--
Regards, __________ James G Roberts
/___ ____ | jrobert@xxxxxxxxxxxxxxxxxxxxx
Jim __ / /___/ / jgroberts@xxxxxxxxxx
/ /_/ /---| | Room: BE436, Hilversum
\____/ /_/ Tel: +31 35 687 4308 Fax: 5976
======================================================================
Peter Arnold wrote:
>
> Johnni,
>
> In response to your original question, the ground planes will be
> automatically connected. Wherever a ground connection occurs in the
> schematic, your layout tool will connect it to both planes. Normally there
> are enough ground connections spread around a board (e.g. at least one per
> decap) that the planes are well stitched together just by this process. You
> might also add GND vias around the board edge every 1/2" for improved EMC,
> it seems to be beneficial.
>
> I have the feeling that there may be a better stackup plan for your project,
> unless you have very special thickness, impedance requirements, restriction
> to those 20-mil cores, etc. As it stands the inner routing layers are close
> to each other but far from their planes, for example. Could you get away
> with just one each of 3V3 and GND plane? (Is 1 ounce of each enough to carry
> the current you need?) Then you could couple power and ground tight in the
> middle.
>
> 1 routing
> 2 routing
> 3 3V3
> 4 GND
> 5 routing
> 6 routing (or GND fill)
>
> Here is another common 6-layer stackup:
>
> 1 routing (or GND fill)
> 2 3V3
> 3 routing
> 4 routing
> 4 GND
> 6 routing
>
> You could bury clocks and high-speed inside the 3V3-GND cavity. If you have
> that GND fill topside you get good power delivery for your high-speed chips
> on the top surface. Depending on your exact needs, there could be many
> optimal solutions.
>
> Regards,
> peter arnold
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Stephane Tremblay
> Sent: Tuesday, October 29, 2002 11:01 AM
> To: johnni.friis@xxxxxxxxx; si-list@xxxxxxxxxxxxx;
> si-list-bounce@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: How to connect to GND planes
>
> Johnni,
>
> I have noticed in your stackup that you have 2 routing layers (#3=
> and #4). If you have signals that are switching from one routing layer to=
> the other, take care: Normally the current return path is the plane=
> underneath the signals (the path with the lowest inductance). So by=
> switching from layer 3 to layer 4 in your stackup, the return path as to=
> switch from one plane to another (in this example from layer 2 to layer
> 5).=
> This as the side effect of increasing impedance of the return path if you=
> don't provide vias near EACH discontinuity on signal layer.=20
>
> If I were you I would place the two signal layers placed "top and bottom"
> of=
> a plane so the return path will not need to change plane whenever you=
> change layer with your signals. This way you minimize signal return path=
> impedance discontinuity. And you will not need to provide tons of GND vias=
> near each discontinuity.
>
> Steph.
>
> At 10:43 AM 10/29/02 +0100, johnni.friis@xxxxxxxxx wrote:
>
> >Hi
> >
> >I have a 6 layer stackup with 2 GND planes, how do I connect the 2 GND
> >planes together ?
> >E.g. what distance should I use between vias ? What is the best patter=3D
> >n to
> >use ?
> >
> >I have a MCU running at 100 MHz (C8051F126 until C8051F122 is relased, =3D
> >from
> >cygnal), a K6R1008V1D (10 ns RAM), and a GAL16LV8-5 (5 ns PLD). And a =3D
> >lol
> >of slower devices.
> >I don't know the edge rates. I don't have a simulator.
> >Address- and controlsignals are source terminated, datasignals are plan=3D
> >ed
> >to be routed as lumped elements. (Tr > 0,5 ns -->> flightlength =3D3D 2.=
> =3D
> >75
> >inch, a faktor of 4, gives a max treaclength of 690 mills).
> >
> >
> >Stackup:
> >
> >Layer1: Components / routing
> >5.1 mill preprik
> >Layer2: GND plane
> >20 mill FR4 core
> >Layer3: routing
> >5.1 mill preprik
> >Layer4: routing
> >20 mill FR4 core
> >Layer5: GND plane
> >5.1 mill preprik
> >Layer6: 3V plane
> >
> >
> >Yours sincerely,
> >
> >Johnni Friis
> >
> >
> >VELUX A/S
> >Accessories
> >
> >B=3DE6kg=3DE5rdsvej 40
> >6900 Skjern
> >
> >
> >Telephone Direct: +45 9980 6326
> >Telephone Office: +45 9735 3511
> >Office FAX: +45 9980 6260
> >
> >e-Mail: johnni.friis@xxxxxxxxx
> >WWW: http://www.VELUX.com
> >
> >=3D
> >
> >
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> ______________________________________________
>
> St=E9phane Tremblay
> Hardware project leader
>
> Matrox Graphics Inc. (MGI)=20
> 1025 St-Regis, Dorval (Quebec), H9P 2T4=20
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