[SI-LIST] Re: High speed signal on top layer
- From: steve weir <weirsi@xxxxxxxxxx>
- To: jkeeble@xxxxxxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 31 May 2005 19:52:20 -0700
John in capping the tracks go on layer 2. ( At least that is the way that
I understand it. ) The microstrip plate up, and SM problems are simply
avoided.
Steve.
At 12:39 PM 6/1/2005 +1000, Jon Keeble wrote:
>I'm still struggling to understand exactly what is "capping", and how it
>differs from simply being another layer, despite Steve's kind attempts to
>explain it.
>
>.. do the tracks remain on the outer layer ie do not require vias?
>
>The particular case that interests me is the multiGbit connections between
>Virtex4 MGT IO and SFP connectors.
>Xilinx have arranged for this to happen on the outer layer, i.e. no vias.
>Is "capping" going to help? i.e. mitigate the uncertainties of outlayer
>plating and soldermask on Zo?
>
>Regards
>
>Jon
>
>
>----- Original Message -----
>From: "Istvan Novak" <istvan.novak@xxxxxxx>
>To: <weirsi@xxxxxxxxxx>
>Cc: <jkeeble@xxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
>Sent: Tuesday, May 31, 2005 11:23 AM
>Subject: Re: [SI-LIST] Re: High speed signal on top layer
>
>
> >
> > Steve, John,
> >
> > Tradeoff with capping is it also means an extra layer (and for symmetry
> > reasons,
> > probably two layers) in the PCB .
> >
> > Regards,
> > Istvan
> >
> >
> > steve weir wrote:
> >
> > >John, that is where dielectric caps the uppermost signal etch. This
> > >controls the copper dimensions, affording much better impedance control.
> > >
> > >Regards,
> > >
> > >Steve.
> > >At 07:41 AM 5/31/2005 +1000, Jon Keeble wrote:
> > >
> > >
> > >>Hi Steve ..
> > >>
> > >>What is 'capping'?
> > >>
> > >>Regards
> > >>
> > >>Jon Keeble
> > >>
> > >>----- Original Message -----
> > >>From: "steve weir" <weirsi@xxxxxxxxxx>
> > >>To: <george_dai@xxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > >>Sent: Tuesday, May 31, 2005 6:49 AM
> > >>Subject: [SI-LIST] Re: High speed signal on top layer
> > >>
> > >>
> > >>
> > >>
> > >>>George,
> > >>>
> > >>>1. Possible, but there are several pitfalls, including control over
> > >>>plate-up and solder mask. Capping could help with those.
> > >>>
> > >>>
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