[SI-LIST] Re: High speed signal on top layer
- From: Larry Miller <ldmiller@xxxxxxx>
- To: george_dai@xxxxxxx
- Date: Mon, 30 May 2005 21:26:44 -0700
George,
On May 30, 2005, at 8:37 PM, George Dai wrote:
> Hi Larry,
>
> Thanks for your comment,
> 1, Currently we limit the delta of the pos/minus signal lentgh to less
> than 50 mil, is that enough? (Per my caculation, it create around 10ps
> different delay)
Should be OK.
> 2, I don't understand the EMI issue very clearly. Do you mean the 3G
> signals will couple to the adjacent power plane, then make EMI? Any
> other pitfalls besides EMI problem?
The signals need to return to the driver via a GND plane. (Most
"differential pairs" are not really differential but are single-ended
signals driven out of phase. For it to be truly differential you
would need transformers, like in Ethernet 100BASE-TX)
If a good GND is opposite your signal traces there is no problem. The
signal currents mirror onto the GND plane and return to the driver.
If your signals are opposite a power plane, then the return currents
mirror onto that plane. However, these currents have to ultimately
get to a GND plane to complete the circuit (Kirchoff's Law). If you
have appreciable impedance between the power plane and the GND plane,
then two things will occur:
1) The signal current IR drop (or, really, IZ since it is usually
complex) will make noise on the power plane. This can get radiated
(EMI).
2) The added impedance between power and GND planes add to the
overall transmission line systems impedance, causing an impedance
mismatch, which in turn causes reflections on your differential
pairs. (SI problems, maybe more noise and EMI.)
At lower frequencies (below 100-200 MHz) you can effectively bypass
power to GND, i.e., create an AC short circuit, with capacitors.
Above this, discrete capacitors do not work well (See si-list for
discussions). Up to 500 or 600 MHz you can create "good" bypass
capacitors by having power and GND planes closely spaced, so you can
maintain a low AC impedance from power to GND.
After you get much above 500 or 600 MHz (in frequency, or, equivalent
rise times) even the power/GND capacitance does not work well. This
is why higher frequency signals use these "differential" pairs-- the
signal currents largely cancel IF they have a "good" DC plane to work
against. Unfortunately, a "good" DC plane means that it has a low
impedance path back to the driver, and most ICs require that this be
a GND plane. This (use a GND plane) is certainly the "safe" way to do
it.
But there are exceptions:
As you get up above 2 GHz, FR-4 PC board material gets so lossy that
the return currents get dissipated rather than returned cleanly to
the IC. If you look at the Fibre Channel physical layer standard (FC-
PI-2 at t11.org), you will see that at 4 GHz they do not require
impedance matching at all! (0 dB S11 return loss.) So if you are
using a good run-length-limited coded serial scheme such as 8B/10B
coding, all of your frequencies will be very high, and you might have
a chance using the power plane for your differential pairs. (You may
have to do a PC board "spin" to verify this.) Most EMI problems these
days seem to be in the 500 MHz - 1 GHz zone, in my observation.
If possible, use Current-Mode Logic (CML) for your 3 GHz signals. It
seems to be much better behaved and tolerant than PECL or LVDS. My
experience, anyway.
Larry Miller
>
> Best Regards,
> George
> ---original message---
> From:Larry Miller ; Mon, 30 May 2005 10:15:19 -0700
> Subject:[SI-LIST] Re: High speed signal on top layer
>
>>
>> On May 30, 2005, at 4:48 AM, George Dai wrote:
>>
>>
>>> Hi all,
>>>
>>> We are layout one 3.0Gbps high speed backplane. The original design
>>> style
>>> is routing the edge coupling differential signals in the internal
>>> layer,
>>> with adjacent GND plane. Now we met the layer limitation, and here
>>> is the
>>> questions,
>>> 1. Can we routing the differential pair on the top layer with GND
>>> plane
>>> on the second layer? In my knowledge, it seems functional but odd.
>>> Please give your advice.
>>>
>>
>> That will work, but you have to be very careful to keep your routes
>> exactly the same length and parallel. If there is any unbalance it
>> radiates. Be sure to take into account the difference in propagation
>> velocity compared to striplines if you have critical timing.
>>
>>
>>> 2. Can we use one continuous power plane (12v or 5v) as the
>>> reference
>>> plane to the high speed signals? For example, if 3.0Gbps signals on
>>> top
>>> layer works, can the second layer be +12v power plane?
>>>
>>
>> I would not do this. It is practically impossible to make the power
>> plane at AC ground (by bypassing or capacitance between planes) at
>> 3G. You would probably have EMI problems.
>>
>> Larry Miller
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