[SI-LIST] Re: High speed signal on top layer
- From: steve weir <weirsi@xxxxxxxxxx>
- To: jkeeble@xxxxxxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 30 May 2005 16:25:35 -0700
John, that is where dielectric caps the uppermost signal etch. This
controls the copper dimensions, affording much better impedance control.
Regards,
Steve.
At 07:41 AM 5/31/2005 +1000, Jon Keeble wrote:
>Hi Steve ..
>
>What is 'capping'?
>
>Regards
>
>Jon Keeble
>
>----- Original Message -----
>From: "steve weir" <weirsi@xxxxxxxxxx>
>To: <george_dai@xxxxxxx>; <si-list@xxxxxxxxxxxxx>
>Sent: Tuesday, May 31, 2005 6:49 AM
>Subject: [SI-LIST] Re: High speed signal on top layer
>
>
> >
> > George,
> >
> > 1. Possible, but there are several pitfalls, including control over
> > plate-up and solder mask. Capping could help with those.
>
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