[SI-LIST] Re: Ground Article
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "'Joel Brown'" <joel@xxxxxxxxxx>
- Date: Wed, 18 Jan 2017 11:16:10 -0800
Well, this is turning out to be a lively discussion!
From: Joel Brown [mailto:joel@xxxxxxxxxx] ;
Sent: Wednesday, January 18, 2017 11:00 AM
To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
Cc: corley@xxxxxxxxx; SI-List <si-list@xxxxxxxxxxxxx>;
si-list-bounce@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Ground Article
Using LDOs to reduce noise from digital sources has been mentioned several
times, I am sure it is a valid technique and use it myself but LDOs typically
only filter noise out to several MHZ. So does that mean noise beyond this
frequency is not a problem or is it taken care of by other means such as bypass
caps? Also I see it is quite common for IC manufacturers to recommend ferrite
beads for sensitive power supplies such as PLLs. I see this a lot from FPGA and
Clock buffer / generator vendors. I don't like doing it for reasons that I
think have already been covered but for the FPGA it cuts up the power planes
into many tiny areas. In a recent design I decided not to use a clock buffer
from manufacturer "I" because they recommended ferrite beads and resistors to
filter the power and chose manufacturer "S" because they said just bypass caps
where fine.
On Wed, Jan 18, 2017 at 10:42 AM, Lee Ritchey <leeritchey@xxxxxxxxxxxxx
<mailto:leeritchey@xxxxxxxxxxxxx> > wrote:
Well put!
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>
[mailto:si-list-bounce@xxxxxxxxxxxxx ;<mailto:si-list-bounce@xxxxxxxxxxxxx> ] On
Behalf Of Chuck Corley
Sent: Wednesday, January 18, 2017 10:28 AM
To: si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx> ;
si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Ground Article
... But noisy power supply rails (feeding digital
circuitry) will not do you well when they also feed sensitive analog.
Thoughts:
Agree with you 100%. Clean power supplies are critical for low-noise
circuits. For 32+ years I've designed sensitive ADCs, DACs, amplifiers and
other analog and digital circuits in measurement instruments for HP,
Agilent, Keithley and National Instruments. When we've hunted down noise
sources on sensitive circuits it's usually from the power supply,
or from external noise coupling onto the power supply.
Basics: Typically for feeding ultra-sensitive analog circuits that want
very low noise levels I follow a switching power supply by a low-noise LDO
(Low Dropout) Linear regulator. The voltage output of the switching supply
needs to be high enough to accommodate the extra headroom needed
by the LDO.
- In addition to using an LDO to reduce power supply noise, there are also
special LDOs that are specifically designed for extra-low noise
output.
- The LDO should be far enough from switching supplies (and their
surrounding input and output caps and components) so that the switcher
circuit can't couple noise into the LDO circuit.
- In extreme low-noise cases separate smaller LDOs that independently feed
separate or isolated RF/analog amplifiers or ADCs/DACs may be required to
isolate noise between circuits. But ... be careful to not go crazy and
start doing this extra-extreme level when it's not really needed.
- Once you make the supply clean, keep it clean! Don't put noisy digital
circuits on the same supply. Don't run that clean low-noise supply on a
plane right up a few mils under another noisy power plane on an adjacent
layer that could couple noise into it. Etc.
Split planes:
So far I still haven't seen a side-by-side comparison where split planes
actually helped (for cases when the board has actually implemented a SOLID
ground plane). Typically I see split planes used for isolation purposes and
then later they find it didn't help or made the noise worse and then went
back to solid planes. Just because someone's done split planes on a design
doesn't mean it actually helped. ;-) One of the side-by-side tests I saw
done was when I was at Cisco/Cerent, after measurements showed the noise had
actually increased by splitting the planes they also went back to merging
the planes back together. I think split planes don't usually help because a
true solid plane is an almost magical thing, normally it's low inductance
makes it hard to accumulate enough of a voltage drop to create significant
high frequency noise between points on the plane. To be clear, I think it's
possible noise could be generated across points on a good solid plane, but
it's fairly hard to generate enough noise to cause a problem if it's a truly
solid
plane.
Now if a plane is NOT solid (one example: Under BGA ICs where the ground
plane has been eaten into too far) then it's not too hard to get enough
voltage across the ground plane to create noise in sensitive circuits, and
that's when people I've talked with said split planes helped. But I think
split planes helped in those cases because they didn't have a truly solid
ground plane in the first place and that's what actually caused the noise
problem.
Chuck Corley
National Instruments
On 2017-01-18 08:50, Kevin G. Rhoads wrote:
On 1/18/2017 9:16 AM, Istvan Novak wrote:
in mixed-signal boards and on some boards where naturally very noisy
circuits (like high-current DC-DC converters) have to coexist with
sensitive circuits, like SerDes, PLLs, etc, splitting the ground
plane between the domains can improve the isolation and thus improves
performance, as long as we make sure that we dont create SI and/or
EMI problems by crossing the splits with signals that otherwise need
a solid reference.
First the disclaimer -- I mostly follow the SI list to learn.
Next the other disclaimer -- the board I speak of is a one-off for
university research use.
We had a multi-use board (i.e., K101) for instrumentation support on
sounding rocket science flights. Among other things, it digitized
three axis analog magnetometer data and formatted that to feed by
synchronous serial to NASA telemetry.
Four layer board
16 bit ADCs
10 MHz synch serial channels (NASA WFF 93 standard) SOLID ground plane
Nominal +28 from NASA batteries through DC-DC for +/-12 and +5 in box
First gen used filtering -- digitized channels fairly noisy -- even
though the +5 was decoupled to death -- distributed decoupling across
the board -- both electrolytics and 0.1 microF-s
Second gen split the +5 supplies -- generating one from +12 via LM7805
and that one supplying the ADCs and +5 op-amp front ends.
MUCH less noise
So -- the SI issues are truly serious. I have nothing to add to that
except solid ground plane with separate power supplies can work well
in some situations. But noisy power supply rails (feeding digital
circuitry) will not do you well when they also feed sensitive analog.
If anyone wants to see the details (links are "public"):
Cascades 2 board photos
https://www.facebook.com/kgrhoads/posts/4915482088395
Cascades 2 instrumentation
http://www.facebook.com/album.php?aid 50033 ;
<http://www.facebook.com/album.php?aid 50033&id38500958&lÂ3c77ba>
&id38500958&lÂ3c77ba
e3
Cascades2 schematics
https://www.facebook.com/media/set/?set=a.4916478913315.1073741831.133
8500958&type=3
Sincerely
Kevin
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