[SI-LIST] Re: Getting Started
- From: Graham Kus <nemisonic@xxxxxxxxx>
- To: Chris Maryan <cmaryan@xxxxxxxxxx>
- Date: Mon, 27 Apr 2009 11:58:41 -0400
Hi Chris,
I empathize with your situation. My group made a similar transition from
SDRAM to DDR and then to DDR2. This is consumer-product land with 4-layer
boards and plastic cases... not an easy place to be.
The "conservative design" you speak of is nebulous concept these days. To
gain some fundamental understanding of the Physics, I would recommend these
texts to get started.
"High Speed Digital Design" (Howard Johnson PhD, Martin Graham PhD)
"Timing Analysis and Simulation for Signal Integrity Engineers" (Greg
Edlund)
"Right the First Time" (Lee Ritchey)
From a tools standpoint:
A tool that can run S-parameter analysis on the PCB layout is a *fantastic*
asset. This can model the physical interconnect to show bandwidth (and
crosstalk) of the transmission lines in the DDR/DDR2 bus (or your
mulit-gigabit SERDES).
For modeling power integrity, a tool should be able to show:
- board resonance / plane resonance
- power supply impedance vs. frequency at a point (such as an IC power-pin)
There are a lot of tools that do this, but our group made the case to get
Sigrity's PowerSI and Speed2k, so I am probably biased. IMO, any EDA vendor
worth their salt will show up and run one of your designs to demonstrate the
tool. In any case, having this kind of simulation flow on hand has resolved
a few situations where a name-brand customer says "it's not our board, it's
your chip!" and we can prove otherwise (diplomatically, of course). The
bottom line is this kind of simulation workflow saves in terms of
"time-to-market."
Good luck,
-Graham
On Fri, Apr 24, 2009 at 5:45 PM, Chris Maryan <cmaryan@xxxxxxxxxx> wrote:
> I recently ran across a project where the power distribution on a
> prototype board was botched, and some SI issues were suspected as well.
> Which got me thinking, how can we prevent this sort of thing in the
> future and get it right the first time? At the moment, our group doesn't
> use any SI or power analysis tools, we've done very well on the basis of
> experience and conservative design.
>
>
> So for all of you out there: what sort of tools should I be looking at
> if I am interested in validating board level power quality and SI? The
> boards are large FPGA based, typically 8-16 layers, with DDR2 layout
> being the main area interest for SI, along with a handful of
> multi-gigabit serial signals. Assume for a moment that things like EMI
> emission and susceptibility and analog circuit noise are (at least for
> the time being) outside of my interest.
>
>
>
> How do I get started?
>
>
>
> Thanks,
>
>
>
> Chris Maryan
>
>
>
>
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