I recently ran across a project where the power distribution on a prototype board was botched, and some SI issues were suspected as well. Which got me thinking, how can we prevent this sort of thing in the future and get it right the first time? At the moment, our group doesn't use any SI or power analysis tools, we've done very well on the basis of experience and conservative design. So for all of you out there: what sort of tools should I be looking at if I am interested in validating board level power quality and SI? The boards are large FPGA based, typically 8-16 layers, with DDR2 layout being the main area interest for SI, along with a handful of multi-gigabit serial signals. Assume for a moment that things like EMI emission and susceptibility and analog circuit noise are (at least for the time being) outside of my interest. How do I get started? Thanks, Chris Maryan ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu