[SI-LIST] Re: FW: AC Blocking capacitor relative positions andreferenceplanevoids
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: Chris Cheng <Chris.Cheng@xxxxxxxx>
- Date: Fri, 20 Nov 2009 19:17:14 -0500
Chris
you are absolutely correct. That is why I said:
"This return loss problem is always more acute
for closely spaced "things" on low loss substrates, and will cause
insertion loss uncertainty along with high frequency ringing."
Chris Cheng wrote:
> Scott,
> If I recalled our off line conversation, I believe one of the problem is if
> we purely just look at the S21 characteristics we will missed out the case
> where the driving or receiving end is not ideally terminated at 50 ohm which
> is likely the case at high gigabit design due to package and circuit
> parasitics. If these caps and pads are placed close enough to the
> receiver/driver the reflections can set up local resonance with each other
> and result in ringing.
> That is the reason why we agreed that placement of the series cap matters in
> the channel even though that shouldn't be if the system is assumed to be
> linear and perfectly terminated.
> Relying purely on S21 without considering the driver/receiver condition is
> not sufficient.
> Regards,
> Chris
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of Scott McMorrow
> Sent: Friday, November 20, 2009 3:19 PM
> To: Lee Ritchey
> Cc: Yuriy Shlepnev; Steve Weir; Robert Haller; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
> andreferenceplanevoids
>
> To Lee and all,
> I'd have to see your measurements and method to speak to your results
> intelligently. It's been a while since I performed capacitor pad
> simulations, optimizations and measurements. The results are similar to
> what Yuriy shows. I currently have a need to do this for a product I am
> designing for a client. This return loss problem is always more acute
> for closely spaced "things" on low loss substrates, and will cause
> insertion loss uncertainty along with high frequency ringing. I have
> have an 0402 capacitor model built in CST (with plates) that has been
> correlated to measurements, which I will use for a few modeling
> experiments. Because the solver has been previously correlated for
> this, and other similar problems, we can agree that it is a valid point
> of comparison. I will report back on the results, and we will try to
> include several examples in our next TRL test vehicle.
>
> Whether or not pad compensation with holes in the underlying planes
> provides significant performance improvements depends upon the
> dielectric thickness between the ground plane, the pads, and the
> location of the lowest plate in the capacitor. In some cases, the
> inductive loop between the capacitor plates and the PCB ground is
> compensated by the excessive pad capacitance, up to reasonably high
> frequencies. This may very well be the case that you happened on in
> your test vehicle. In that case, your conclusions may quite valid.
>
> For others that may wish to try holes in the plane, be aware that
> without a modeling environment and method that has been correlated to
> measurements, you risk making your design worse. Placing holes in
> ground planes is not for the weak of heart. It's best not to generalize
> these sorts of design practices.
>
> Regards,
>
> Scott
>
>
>
> Lee Ritchey wrote:
>
>> Yuriy,
>>
>> I have measured data that trumps simulations every day. The reason I
>> haven't published the data on this forum is it is contained in a large
>> report that cannot be sent as an attachment.
>>
>> In virtually all cases, AC coupling capacitors are connected into nets
>> using vias and surface mount pads. You are correct that the capacitance of
>> these vias completely hides any effects of the mounting pads. The tests I
>> have run are on nets with capacitors so mounted and the loss vs frequency
>> measurements made up to 6 GHz. There is no detectable affect on this
>> measurement with identical nets with and without the AC capacitors. The
>> vias are 12 mil drill through a 100 mil thick PCB. There was no clearing
>> of the planes under the capacitor mounting pads.
>>
>> >From this two conclusions can be drawn:
>>
>> 1. The disruptions associated with the vias and mounting pads is not
>> significant, so why complicate the design job by insisting on extra artwork
>> effort.
>>
>> 2. Since the disruptions are not significant, the physical location of the
>> AC capacitor along the length of the path is not important. This had been
>> pointed out by others on this forum such as Scott McMorrow.
>>
>> In general, I trust no simulations that are not validated with
>> measurements, nor should anyone else. Until there is proof that the
>> simulation model accurately represents the real circuit it should not be
>> trusted. That is why I build so many test PCBs. I need to prove to my
>> clients that the advice I am giving them is valid. After all, some of them
>> bet in excess of $100 Million on this advice and it needs to be right.
>>
>> Anyone else who gives advice based solely on simulations needs to add that
>> caveat to their advice.
>>
>> Anyone who gives advice simply because it is published in an applications
>> note is in the same position. We all know how erroneous most application
>> notes are.
>>
>> Lee Ritchey
>>
>>
>>
>>
>>> [Original Message]
>>> From: Yuriy Shlepnev <shlepnev@xxxxxxxxxxxxx>
>>> To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>; Steve Weir <weirsi@xxxxxxxxxx>
>>> Cc: Robert Haller <rhaller@xxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
>>> Date: 11/20/2009 12:40:31 PM
>>> Subject: RE: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
>>>
>>>
>> andreferenceplanevoids
>>
>>
>>> Lee,
>>>
>>> I would like to investigate your board with the AC caps numerically and
>>> publish the results on SI list. Please send me brd or mcm file and point
>>>
>>>
>> at
>>
>>
>>> the nets to simulate.
>>>
>>> In general, the effect of the voids under AC caps may be not important, if
>>> the pads are small or there are larger discontinuities in the channel.
>>>
>>>
>> Vias
>>
>>
>>> on both sides from the AC cap pads may be such larger discontinuity. Any
>>> optimization of the pads may not provide any visible improvement because
>>>
>>>
>> of
>>
>>
>>> the vias. Smaller capacitor footprint and longer line segments may also
>>>
>>>
>> lead
>>
>>
>>> to lower reflections and make the optimization useless - see for instance
>>> 0402 case in
>>> http://www.simberian.com/AppNotes/AC_CouplingCapacitors_2008_04.pdf (slide
>>> 15 - the reflection in non-optimized case is about -20 dB that may be
>>>
>>>
>> hardly
>>
>>
>>> noticeable on TDR). However, the larger footprint like 0603 on slide 16
>>>
>>>
>> with
>>
>>
>>> the original reflection above -10 dB should be clearly visible on TDR. The
>>> reflection in this case will depend on the position of the caps in the
>>> channel. Again, the larger discontinuities like vias may obfuscate the
>>> effect. There is always some advantage in the optimization, but the
>>>
>>>
>> overall
>>
>>
>>> effect may depend on a particular net.
>>>
>>> Best regards,
>>> Yuriy Shlepnev
>>> www.simberian.com
>>>
>>>
>>> -----Original Message-----
>>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>>
>>>
>> On
>>
>>
>>> Behalf Of Lee Ritchey
>>> Sent: Friday, November 20, 2009 9:28 AM
>>> To: Steve Weir
>>> Cc: Robert Haller; si-list@xxxxxxxxxxxxx
>>> Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
>>> andreferenceplanevoids
>>>
>>> Steve,
>>>
>>> I thought you said you had seen this phenomena and would share your
>>>
>>>
>> results
>>
>>
>>> with us. Isn't that what you stated in one of your replies?
>>>
>>> I'm willing to share my results with anyone who wants to send me a
>>> request. I may regret this offer if I get too many requests!
>>>
>>> Lee Ritchey
>>>
>>>
>>>
>>>
>>>> [Original Message]
>>>> From: steve weir <weirsi@xxxxxxxxxx>
>>>> To: <leeritchey@xxxxxxxxxxxxx>
>>>> Cc: Robert Haller <rhaller@xxxxxxxxxxxxx>; si-list@xxxxxxxxxxxxx
>>>>
>>>>
>>> <si-list@xxxxxxxxxxxxx>
>>>
>>>
>>>> Date: 11/19/2009 5:40:45 PM
>>>> Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
>>>>
>>>>
>>> andreferenceplanevoids
>>>
>>>
>>>> Lee, sure we can do that. I think it would be educational all the way
>>>> around. I'd like to see the PCB files first. Are they available in
>>>> Allegro?
>>>>
>>>> Best Regards,
>>>>
>>>>
>>>> Steve.
>>>> Lee Ritchey wrote:
>>>>
>>>>
>>>>> I'd like to see that as my measurements don't show any significant
>>>>>
>>>>>
>>> impact.
>>>
>>>
>>>>> I've got test PCBs that can used to check.
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>> [Original Message]
>>>>>> From: steve weir <weirsi@xxxxxxxxxx>
>>>>>> To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
>>>>>> Cc: Robert Haller <rhaller@xxxxxxxxxxxxx>; si-list@xxxxxxxxxxxxx
>>>>>>
>>>>>>
>>>>>>
>>>>> <si-list@xxxxxxxxxxxxx>
>>>>>
>>>>>
>>>>>
>>>>>> Date: 11/18/2009 7:49:18 PM
>>>>>> Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
>>>>>>
>>>>>>
>>>>>>
>>>>> andreferenceplane voids
>>>>>
>>>>>
>>>>>
>>>>>> Lee, the difference is readily seen in VNA measurements. Depending
>>>>>>
>>>>>>
>> on
>>
>>
>>>>>> the signal spectra the eye is visibly impacted.
>>>>>>
>>>>>> Best Regards,
>>>>>>
>>>>>>
>>>>>> Steve.
>>>>>> Lee Ritchey wrote:
>>>>>>
>>>>>>
>>>>>>
>>>>>>> This could be one of those cases where the effect was visible, but
>>>>>>>
>>>>>>>
>> not
>>
>>
>>>>>>> significant.
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>> [Original Message]
>>>>>>>> From: Haller, Robert <rhaller@xxxxxxxxxxxxx>
>>>>>>>> To: si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>
>>>>>>>> Date: 11/18/2009 1:34:29 PM
>>>>>>>> Subject: [SI-LIST] FW: AC Blocking capacitor relative positions
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>> andreference plane voids
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>> JF,
>>>>>>>> Depending on your specific high speed link requirements, voids
>>>>>>>>
>>>>>>>>
>> under
>>
>>
>>>>>>>>
>>>>> the
>>>>>
>>>>>
>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>> capacitors are an easy way to reduce the impedance discontinuity. We
>>>>>>>
>>>>>>>
>>>>>>>
>>>>> model
>>>>>
>>>>>
>>>>>
>>>>>>> this with a 3D Full Wave field solver. We also built up some
>>>>>>>
>>>>>>>
>>> structures
>>>
>>>
>>>>>>>
>>>>> in
>>>>>
>>>>>
>>>>>
>>>>>>> the lab and measured them (both in time and frequency Domains).
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>> We were pleasantly surprised how much the reliefs helped and how
>>>>>>>>
>>>>>>>>
>> well
>>
>>
>>>>>>>>
>>>>> the
>>>>>
>>>>>
>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>> correlation to tools were. I wouldn't worry about the difference
>>>>>>>
>>>>>>>
>>>>>>>
>>>>> between a
>>>>>
>>>>>
>>>>>
>>>>>>> two cutouts versus a single void. If you can make the capacitor look
>>>>>>>
>>>>>>>
>>>>>>>
>>>>> like a
>>>>>
>>>>>
>>>>>
>>>>>>> 100Ohm transmission line (with no impedance discontinuity) then the
>>>>>>> placement isn't critical, but in practice it depends. I have seen
>>>>>>>
>>>>>>>
>>> some
>>>
>>>
>>>>>>> vendors specify lengths to avoid, because if the package length plus
>>>>>>> distance to the cap (and the associated discontinuity) are a
>>>>>>>
>>>>>>>
>> multiple
>>
>>
>>> of
>>>
>>>
>>>>>>> the UI (unit interval of the LINK) undesirable resonances can occur.
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>> Regards
>>>>>>>> Bob Haller
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> -----Original Message-----
>>>>>>>> From: si-list-bounce@xxxxxxxxxxxxx
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>>>>
>>>>>
>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>> On Behalf Of jean-francois hasson
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>> Sent: Wednesday, November 18, 2009 4:04 PM
>>>>>>>> To: si-list@xxxxxxxxxxxxx
>>>>>>>> Subject: [SI-LIST] AC Blocking capacitor relative positions and
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>> reference
>>>>>
>>>>>
>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>> plane voids
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>> Hi,
>>>>>>>>
>>>>>>>> When looking at AC coupling capacitors on high speed serial links
>>>>>>>>
>>>>>>>>
>> it
>>
>>
>>>>>>>>
>>>>> is
>>>>>
>>>>>
>>>>>
>>>>>>>> often recommended to void the reference plane under these
>>>>>>>>
>>>>>>>>
>> capacitors
>>
>>
>>>>>>>>
>>>>> to
>>>>>
>>>>>
>>>>>
>>>>>>>> minimize capacitance variations. Most of the times, in the designs
>>>>>>>>
>>>>>>>>
>> I
>>
>>
>>>>>>>> have seen, the void is exactly underneath each AC blocking
>>>>>>>>
>>>>>>>>
>> capacitor
>>
>>
>>>>>>>> including landing pads. If ever the capacitors were quite close,
>>>>>>>>
>>>>>>>>
>>> would
>>>
>>>
>>>>>>>> there be any reason why a single void below both capacitors would
>>>>>>>>
>>>>>>>>
>> be
>>
>>
>>>>>>>>
>>>>> an
>>>>>
>>>>>
>>>>>
>>>>>>>> issue ? I have also noticed that most of the times AC blocking
>>>>>>>> capacitors are not as close as possible to a transmitter or
>>>>>>>>
>>>>>>>>
>> receiver
>>
>>
>>>>>>>> where I thought it was beneficial to do so to remove the number of
>>>>>>>> impedance disruptions ? Could anyone provide me with some
>>>>>>>>
>>>>>>>>
>>> explanation ?
>>>
>>>
>>>>>>>> Best regards,
>>>>>>>>
>>>>>>>> JF
>>>>>>>>
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>
> --
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> (401) 284-1827 Business
> (401) 284-1840 Fax
>
> http://www.teraspeed.com
>
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