[SI-LIST] Re: FW: AC Blocking capacitor relative positions andreferenceplanevoids
- From: "Lakshmi N. Sundararajan - PTU" <lakshmi.s@xxxxxxxxxxx>
- To: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>, "Yuriy Shlepnev" <shlepnev@xxxxxxxxxxxxx>, "Steve Weir" <weirsi@xxxxxxxxxx>
- Date: Fri, 20 Nov 2009 15:22:47 -0800
Lee,
You say..
" The tests I
have run are on nets with capacitors so mounted and the loss vs frequency
measurements made up to 6 GHz. "
Maybe these voids become more necessary when the frequency is above 6GHz?
I have seen this layout requirement coming from the IC vendor for a 10Ghz
transceivers.
Currently we are using 6Ghz transceivers in production without this void and
are seeing good margins.
Thanks,
-LN
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Lee Ritchey
Sent: Friday, November 20, 2009 2:24 PM
To: Yuriy Shlepnev; Steve Weir
Cc: Robert Haller; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
andreferenceplanevoids
Yuriy,
I have measured data that trumps simulations every day. The reason I
haven't published the data on this forum is it is contained in a large
report that cannot be sent as an attachment.
In virtually all cases, AC coupling capacitors are connected into nets
using vias and surface mount pads. You are correct that the capacitance of
these vias completely hides any effects of the mounting pads. The tests I
have run are on nets with capacitors so mounted and the loss vs frequency
measurements made up to 6 GHz. There is no detectable affect on this
measurement with identical nets with and without the AC capacitors. The
vias are 12 mil drill through a 100 mil thick PCB. There was no clearing
of the planes under the capacitor mounting pads.
From this two conclusions can be drawn:
1. The disruptions associated with the vias and mounting pads is not
significant, so why complicate the design job by insisting on extra artwork
effort.
2. Since the disruptions are not significant, the physical location of the
AC capacitor along the length of the path is not important. This had been
pointed out by others on this forum such as Scott McMorrow.
In general, I trust no simulations that are not validated with
measurements, nor should anyone else. Until there is proof that the
simulation model accurately represents the real circuit it should not be
trusted. That is why I build so many test PCBs. I need to prove to my
clients that the advice I am giving them is valid. After all, some of them
bet in excess of $100 Million on this advice and it needs to be right.
Anyone else who gives advice based solely on simulations needs to add that
caveat to their advice.
Anyone who gives advice simply because it is published in an applications
note is in the same position. We all know how erroneous most application
notes are.
Lee Ritchey
> [Original Message]
> From: Yuriy Shlepnev <shlepnev@xxxxxxxxxxxxx>
> To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>; Steve Weir <weirsi@xxxxxxxxxx>
> Cc: Robert Haller <rhaller@xxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 11/20/2009 12:40:31 PM
> Subject: RE: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
andreferenceplanevoids
>
> Lee,
>
> I would like to investigate your board with the AC caps numerically and
> publish the results on SI list. Please send me brd or mcm file and point
at
> the nets to simulate.
>
> In general, the effect of the voids under AC caps may be not important, if
> the pads are small or there are larger discontinuities in the channel.
Vias
> on both sides from the AC cap pads may be such larger discontinuity. Any
> optimization of the pads may not provide any visible improvement because
of
> the vias. Smaller capacitor footprint and longer line segments may also
lead
> to lower reflections and make the optimization useless - see for instance
> 0402 case in
> http://www.simberian.com/AppNotes/AC_CouplingCapacitors_2008_04.pdf (slide
> 15 - the reflection in non-optimized case is about -20 dB that may be
hardly
> noticeable on TDR). However, the larger footprint like 0603 on slide 16
with
> the original reflection above -10 dB should be clearly visible on TDR. The
> reflection in this case will depend on the position of the caps in the
> channel. Again, the larger discontinuities like vias may obfuscate the
> effect. There is always some advantage in the optimization, but the
overall
> effect may depend on a particular net.
>
> Best regards,
> Yuriy Shlepnev
> www.simberian.com
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
> Behalf Of Lee Ritchey
> Sent: Friday, November 20, 2009 9:28 AM
> To: Steve Weir
> Cc: Robert Haller; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
> andreferenceplanevoids
>
> Steve,
>
> I thought you said you had seen this phenomena and would share your
results
> with us. Isn't that what you stated in one of your replies?
>
> I'm willing to share my results with anyone who wants to send me a
> request. I may regret this offer if I get too many requests!
>
> Lee Ritchey
>
>
> > [Original Message]
> > From: steve weir <weirsi@xxxxxxxxxx>
> > To: <leeritchey@xxxxxxxxxxxxx>
> > Cc: Robert Haller <rhaller@xxxxxxxxxxxxx>; si-list@xxxxxxxxxxxxx
> <si-list@xxxxxxxxxxxxx>
> > Date: 11/19/2009 5:40:45 PM
> > Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
> andreferenceplanevoids
> >
> > Lee, sure we can do that. I think it would be educational all the way
> > around. I'd like to see the PCB files first. Are they available in
> > Allegro?
> >
> > Best Regards,
> >
> >
> > Steve.
> > Lee Ritchey wrote:
> > > I'd like to see that as my measurements don't show any significant
> impact.
> > > I've got test PCBs that can used to check.
> > >
> > >
> > >
> > >> [Original Message]
> > >> From: steve weir <weirsi@xxxxxxxxxx>
> > >> To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
> > >> Cc: Robert Haller <rhaller@xxxxxxxxxxxxx>; si-list@xxxxxxxxxxxxx
> > >>
> > > <si-list@xxxxxxxxxxxxx>
> > >
> > >> Date: 11/18/2009 7:49:18 PM
> > >> Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
> > >>
> > > andreferenceplane voids
> > >
> > >> Lee, the difference is readily seen in VNA measurements. Depending
on
> > >> the signal spectra the eye is visibly impacted.
> > >>
> > >> Best Regards,
> > >>
> > >>
> > >> Steve.
> > >> Lee Ritchey wrote:
> > >>
> > >>> This could be one of those cases where the effect was visible, but
not
> > >>> significant.
> > >>>
> > >>>
> > >>>
> > >>>
> > >>>> [Original Message]
> > >>>> From: Haller, Robert <rhaller@xxxxxxxxxxxxx>
> > >>>> To: si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>
> > >>>> Date: 11/18/2009 1:34:29 PM
> > >>>> Subject: [SI-LIST] FW: AC Blocking capacitor relative positions
> > >>>>
> > >>>>
> > >>> andreference plane voids
> > >>>
> > >>>
> > >>>> JF,
> > >>>> Depending on your specific high speed link requirements, voids
under
> > >>>>
> > > the
> > >
> > >>>>
> > >>>>
> > >>> capacitors are an easy way to reduce the impedance discontinuity. We
> > >>>
> > > model
> > >
> > >>> this with a 3D Full Wave field solver. We also built up some
> structures
> > >>>
> > > in
> > >
> > >>> the lab and measured them (both in time and frequency Domains).
> > >>>
> > >>>
> > >>>> We were pleasantly surprised how much the reliefs helped and how
well
> > >>>>
> > > the
> > >
> > >>>>
> > >>>>
> > >>> correlation to tools were. I wouldn't worry about the difference
> > >>>
> > > between a
> > >
> > >>> two cutouts versus a single void. If you can make the capacitor look
> > >>>
> > > like a
> > >
> > >>> 100Ohm transmission line (with no impedance discontinuity) then the
> > >>> placement isn't critical, but in practice it depends. I have seen
> some
> > >>> vendors specify lengths to avoid, because if the package length plus
> > >>> distance to the cap (and the associated discontinuity) are a
multiple
> of
> > >>> the UI (unit interval of the LINK) undesirable resonances can occur.
> > >>>
> > >>>
> > >>>> Regards
> > >>>> Bob Haller
> > >>>>
> > >>>>
> > >>>>
> > >>>> -----Original Message-----
> > >>>> From: si-list-bounce@xxxxxxxxxxxxx
> > >>>>
> > > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > >
> > >>>>
> > >>>>
> > >>> On Behalf Of jean-francois hasson
> > >>>
> > >>>
> > >>>> Sent: Wednesday, November 18, 2009 4:04 PM
> > >>>> To: si-list@xxxxxxxxxxxxx
> > >>>> Subject: [SI-LIST] AC Blocking capacitor relative positions and
> > >>>>
> > > reference
> > >
> > >>>>
> > >>>>
> > >>> plane voids
> > >>>
> > >>>
> > >>>> Hi,
> > >>>>
> > >>>> When looking at AC coupling capacitors on high speed serial links
it
> > >>>>
> > > is
> > >
> > >>>> often recommended to void the reference plane under these
capacitors
> > >>>>
> > > to
> > >
> > >>>> minimize capacitance variations. Most of the times, in the designs
I
> > >>>> have seen, the void is exactly underneath each AC blocking
capacitor
> > >>>> including landing pads. If ever the capacitors were quite close,
> would
> > >>>> there be any reason why a single void below both capacitors would
be
> > >>>>
> > > an
> > >
> > >>>> issue ? I have also noticed that most of the times AC blocking
> > >>>> capacitors are not as close as possible to a transmitter or
receiver
> > >>>> where I thought it was beneficial to do so to remove the number of
> > >>>> impedance disruptions ? Could anyone provide me with some
> explanation ?
> > >>>>
> > >>>> Best regards,
> > >>>>
> > >>>> JF
> > >>>>
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