[SI-LIST] Re: FW: AC Blocking capacitor relative positions andreferenceplanevoids
- From: "Joel Brown" <joel@xxxxxxxxxx>
- To: <John.Foster@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 20 Nov 2009 12:00:06 -0800
So does this mean I should be putting a 25 mil plane cutout under all 0402
caps used in high speed serial links? Wouldn't the optimal cutout size be
dependent on the thickness of dielectric between the signal and plane layers
and therefore need to be modeled with a 3D solver?
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of John.Foster@xxxxxxxxxx
Sent: Friday, November 20, 2009 10:24 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
andreferenceplanevoids
There was an article in circuit tree a while back that shares some
results on this.
http://www.circuitree.com/Articles/Cover_Story/BNP_GUID_9-5-2006_A_10000
000000000538966
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Lee Ritchey
Sent: Friday, November 20, 2009 9:28 AM
To: Steve Weir
Cc: Robert Haller; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
andreferenceplanevoids
Steve,
I thought you said you had seen this phenomena and would share your
results
with us. Isn't that what you stated in one of your replies?
I'm willing to share my results with anyone who wants to send me a
request. I may regret this offer if I get too many requests!
Lee Ritchey
> [Original Message]
> From: steve weir <weirsi@xxxxxxxxxx>
> To: <leeritchey@xxxxxxxxxxxxx>
> Cc: Robert Haller <rhaller@xxxxxxxxxxxxx>; si-list@xxxxxxxxxxxxx
<si-list@xxxxxxxxxxxxx>
> Date: 11/19/2009 5:40:45 PM
> Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
andreferenceplanevoids
>
> Lee, sure we can do that. I think it would be educational all the way
> around. I'd like to see the PCB files first. Are they available in
> Allegro?
>
> Best Regards,
>
>
> Steve.
> Lee Ritchey wrote:
> > I'd like to see that as my measurements don't show any significant
impact.
> > I've got test PCBs that can used to check.
> >
> >
> >
> >> [Original Message]
> >> From: steve weir <weirsi@xxxxxxxxxx>
> >> To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
> >> Cc: Robert Haller <rhaller@xxxxxxxxxxxxx>; si-list@xxxxxxxxxxxxx
> >>
> > <si-list@xxxxxxxxxxxxx>
> >
> >> Date: 11/18/2009 7:49:18 PM
> >> Subject: [SI-LIST] Re: FW: AC Blocking capacitor relative positions
> >>
> > andreferenceplane voids
> >
> >> Lee, the difference is readily seen in VNA measurements. Depending
on
> >> the signal spectra the eye is visibly impacted.
> >>
> >> Best Regards,
> >>
> >>
> >> Steve.
> >> Lee Ritchey wrote:
> >>
> >>> This could be one of those cases where the effect was visible, but
not
> >>> significant.
> >>>
> >>>
> >>>
> >>>
> >>>> [Original Message]
> >>>> From: Haller, Robert <rhaller@xxxxxxxxxxxxx>
> >>>> To: si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>
> >>>> Date: 11/18/2009 1:34:29 PM
> >>>> Subject: [SI-LIST] FW: AC Blocking capacitor relative positions
> >>>>
> >>>>
> >>> andreference plane voids
> >>>
> >>>
> >>>> JF,
> >>>> Depending on your specific high speed link requirements, voids
under
> >>>>
> > the
> >
> >>>>
> >>>>
> >>> capacitors are an easy way to reduce the impedance discontinuity.
We
> >>>
> > model
> >
> >>> this with a 3D Full Wave field solver. We also built up some
structures
> >>>
> > in
> >
> >>> the lab and measured them (both in time and frequency Domains).
> >>>
> >>>
> >>>> We were pleasantly surprised how much the reliefs helped and how
well
> >>>>
> > the
> >
> >>>>
> >>>>
> >>> correlation to tools were. I wouldn't worry about the difference
> >>>
> > between a
> >
> >>> two cutouts versus a single void. If you can make the capacitor
look
> >>>
> > like a
> >
> >>> 100Ohm transmission line (with no impedance discontinuity) then
the
> >>> placement isn't critical, but in practice it depends. I have seen
some
> >>> vendors specify lengths to avoid, because if the package length
plus
> >>> distance to the cap (and the associated discontinuity) are a
multiple
of
> >>> the UI (unit interval of the LINK) undesirable resonances can
occur.
> >>>
> >>>
> >>>> Regards
> >>>> Bob Haller
> >>>>
> >>>>
> >>>>
> >>>> -----Original Message-----
> >>>> From: si-list-bounce@xxxxxxxxxxxxx
> >>>>
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> >
> >>>>
> >>>>
> >>> On Behalf Of jean-francois hasson
> >>>
> >>>
> >>>> Sent: Wednesday, November 18, 2009 4:04 PM
> >>>> To: si-list@xxxxxxxxxxxxx
> >>>> Subject: [SI-LIST] AC Blocking capacitor relative positions and
> >>>>
> > reference
> >
> >>>>
> >>>>
> >>> plane voids
> >>>
> >>>
> >>>> Hi,
> >>>>
> >>>> When looking at AC coupling capacitors on high speed serial links
it
> >>>>
> > is
> >
> >>>> often recommended to void the reference plane under these
capacitors
> >>>>
> > to
> >
> >>>> minimize capacitance variations. Most of the times, in the
designs I
> >>>> have seen, the void is exactly underneath each AC blocking
capacitor
> >>>> including landing pads. If ever the capacitors were quite close,
would
> >>>> there be any reason why a single void below both capacitors would
be
> >>>>
> > an
> >
> >>>> issue ? I have also noticed that most of the times AC blocking
> >>>> capacitors are not as close as possible to a transmitter or
receiver
> >>>> where I thought it was beneficial to do so to remove the number
of
> >>>> impedance disruptions ? Could anyone provide me with some
explanation ?
> >>>>
> >>>> Best regards,
> >>>>
> >>>> JF
> >>>>
> >>>>
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