A thought I have is this spacing is a spacing to enhance tight localization
while also not impacting impedance or establishing any measurable coupling,
correct? Thanks for the post Scott. The next issue at the high
frequencies (70GHz) is when the distances become too large from strip to
plane you also end up with a large cavity that resonates at frequencies
above or around 70GHz, but still eats SI margin below 70GHz. For our 112G
test fixtures (70GHz desired SI) we run HFSS to over 100GHz to analyze
issues than impact below 70GHz. HFSS has a nifty Eigenmode analysis that I
haven't figured out, which is much faster than running freq stepped
simulations. It only identifies the resonant modes.
- Al
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf
Of Scott McMorrow
Sent: Wednesday, July 3, 2019 12:26 PM
To: Scott McMorrow <Scott@xxxxxxxxxxxxx>; Chris.Cotton@xxxxxxxxxxx;
farhilltramper@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: [EXTERNAL] The gap b/w stitching vias and tline in
serpentine routing
To be clear
1) take the maximum single dielectric thickness on either the top or bottom
of the stripline.
2) Multiply that distance by 4
3) This is the minimum clearance required from trace edge to via pad edge
(even if you use non-essential pad removal)
At this distance, the via is essentially invisible to the signal trace. One
member of the Samtec team went through this exercise just this past month in
order to establish our PCB test board design rules.
Scott McMorrow, CTO Signal Integrity Group Samtec Office 401-284-1827 |
+1-800-726-8329 www.samtec.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf
Of Scott McMorrow
Sent: Wednesday, July 3, 2019 2:21 PM
To: Chris.Cotton@xxxxxxxxxxx; farhilltramper@xxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: [EXTERNAL] The gap b/w stitching vias and tline in
serpentine routing
For symmetric stripline a clearance of 4 times the thickness of the
dielectric from trace to plane works from trace edge to via pad edge. This
has been verified through EM modeling with HFSS to 70 GHz
Scott McMorrow, CTO Signal Integrity Group Samtec Office 401-284-1827 |
+1-800-726-8329 www.samtec.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf
Of Cotton, Chris
Sent: Wednesday, July 3, 2019 2:08 PM
To: farhilltramper@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: [EXTERNAL] The gap b/w stitching vias and tline in
serpentine routing
Hi Tramp,
I think it is difficult to answer your question as there are many missing
details such as frequency of interest, spacing relative to dielectric
height, etc. Also, what kind of SNR are you trying to achieve? Is this a
digital or analog/RF application. Generally for digital applications, if you
have the luxury of sufficient spacing to aggressors then forget the GND vias
and the spacing will suffice.
Best regards,
Chris
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf
Of Tramp
Sent: Wednesday, July 3, 2019 7:36 AM
To: si-list@xxxxxxxxxxxxx
Subject: [EXTERNAL] [SI-LIST] The gap b/w stitching vias and tline in
serpentine routing
[EXTERNAL SENDER: This email originated from outside of Stratus
Technologies. Do not click links or open attachments unless you recognize
the sender and know the content is safe.]
Dear SIlisters,
I did some quick sims sweeping different gaps b/w the stitching ground vias
and tline (Note here the gap refers to the spacing b/w the via and the
tline, not two adjacent ground vias for which I set to twentith lambda)
using 2.5D tool and the results are almost the same. Does anyone have this
experience, such as whether I need to do the sim in 3D, or what distance is
recommended? I saw some implementations put the via at the distance of
merely 4mil while the others do it w/ 20mil. So how on earth is the impact?
--
Best Regards,
Tramp
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