[SI-LIST] Re: ESD simulations
- From: Adeel AHMAD <adeel.ahmad@xxxxxx>
- To: starsilic@xxxxxxxxx
- Date: Wed, 29 Nov 2006 15:16:58 +0530
Hello Canes,
Yafei has rightly pointed out that "ESD test on silicon is the final proof."
however if you HAVE to ensure some level of comfort regarding ESD immunity of
your chip, you may proceed as follows-
1. you need to know what type of ESD clamps are used in your IOs and the ESD
scheme they follow.
typical ones are MosfetRC clamps used for discharge path from power-to-ground,
diodes for discharge path from gnd-to-pwr,
and Parasitic BJT (MOSFET in snapback mode).
2. if MOSFET is used in snapback mode then there is not much you can do because
typically the parasitic bjt formed under mosfet are NOT modelled. the pn
junctions are rather modeled as distinct S-Bulk & D-Bulk diodes. here you can
rely only on data provided by fab regarding behaviour in snapback mode.
simulations will not show you any current path. Typically the Fab does provide
the snapback voltage and hold voltage values that can be used to manually
calculate voltages at various nodes.
3. Diodes too are not typically modelled in forward bias region for currents of
order of 1A(typical in ESD), the region of interest. However, since diodes are
typically the most robust of all ESD clamping devices and quite "forgiving", we
need to see the turn on voltage of diode and the series resistance it provides.
Perimeter of diodes is the parameter we maximise along with some layout
considerations to ensure sufficient current capability. Parasitic diodes
present under mosfets also provide discharge paths and may be taken into
account.
4. RC clamp is the only device you can simulate to a good extent. If that is
present you can create a HBM testbench in hspice, simulate the clamp and note
how much potential is generated at the node. width of mosfet can be decided
based on maximum potential you have in your budgeting.
5. Once we have at least some information on turn-on voltage/hold
voltage/RCclamp voltage, we need to draw complete ESD scheme for the chip.
There must exist "sufficiently low " resistance path for ESD discharge between
every pair of pins present in the chip both in terms of physical spacing and
resistance.The point here is to ensure that voltages produced NO node must
exceed the "prescribed" limits.
This "prescribed" limits are typically determined by the S/D-Bulk pn junction
avalanche breakdown values. This is so because any high voltage develaped at
any node/pin will stress the reverse biased pn junction of RC clampMOSFET/diode.
6. The metal resistance encountered for every pin pair path ( multiplied by HBm
current) needs to be added to get realisitic node voltages.
7. Physical separation of clamps are important.
8. it must be ensured that NO pin is directly connected to gate of mosfet,
without a series resistor in place.
thats the best you can do. and then hope for the best ON SILICON.
-adeel ahmad
[SI-LIST] ESD simulations
* From: Canes Venatici <starsilic@xxxxxxxxx>
* To: si-list@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
* Date: Mon, 27 Nov 2006 02:50:26 -0800 (PST)
Hi all,
Is it possible to do ESD simulation of I/O pad using H-spice.
Should we use process/device simulators like T-CAD (Synopsys) for
this.
How can we say the device fails due to ESD, by simulation.
In essence how can we say a particular i/o pad is ESD proof.
Any help is strongly appreciated,
Canes
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