[SI-LIST] Re: ESD simulations

  • From: Yafei Bi <yafei_bi@xxxxxxxxx>
  • To: starsilic@xxxxxxxxx, si-list@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Mon, 27 Nov 2006 10:01:49 -0800 (PST)

if you have the device model for the ESD protection devices/network, then y=
ou can build the test benches for ESD event(HBM, CBM etc.), and simulate ES=
D event/compliance in HSpice. That will give you some idea on whether the I=
/O design can meet the ESD requirement or not.=0A=0AIf you don't have ESD d=
evice model, then you have to use T-CAD to generate the I-V characteristic =
of the protection devices. Hopely you can do the same experiment on the dev=
ice and see the difference.=0A=0AEventually, ESD test on silicon is the fin=
al proof.=0A=0Abest,=0A=0AYafei=0A=0A----- Original Message ----=0AFrom: Ca=
nes Venatici <starsilic@xxxxxxxxx>=0ATo: si-list@xxxxxxxxxxxxx; si-list@fre=
elists.org=0ASent: Monday, November 27, 2006 2:50:26 AM=0ASubject: [SI-LIST=
] ESD simulations=0A=0AHi all,=0AIs it possible to do ESD simulation of I/O=
 pad using H-spice. =0AShould we use process/device simulators like T-CAD (=
Synopsys) for=0Athis.=0AHow can we say the device fails due to ESD, by simu=
lation.=0AIn essence how can we say a particular i/o pad is ESD proof.=0AAn=
y help is strongly appreciated,=0ACanes=0A=0A=0A=0A=0A =0A_________________=
___________________________________________________________________=0ADo yo=
u Yahoo!?=0AEveryone is raving about the all-new Yahoo! Mail beta.=0Ahttp:/=
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