[SI-LIST] Re: ESD simulations

  • From: Canes Venatici <starsilic@xxxxxxxxx>
  • To: vats123@xxxxxxxxx, si-list@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Tue, 28 Nov 2006 23:14:21 -0800 (PST)

Thanks for all responses,
Srivats Partha,
I agree with you. If we have to design ESD protection for a circuit, we need to 
do get the characteristics
in those regions and that helps in optimizing the protection circuit 
parameters. If I'm wrong please correct it.
But since the I/O pads does have the ESD protection circuits, we can still 
simulate them using HSPICE. 
As the protection devices responds to the ESD pulses, we may need to find 
whether they did the 
correct job (How to quantify it?,  Thats exactly my question). 
As per (A Chip-level Electrostatic Discharge Simulation Strategy) paper, they 
suggest to check the voltage at the nodes of clamping paths, whether they 
exceeded the threshold (I don't know what value we can assume). 
I feel from any pin to any pin the resistance should be within some threshold 
during ESD (HBM/MM/CDM)
(I don't know how to have a reasonable value, probably its given for a 
technology from vendors for their I/Os).

Yafei Bi,
Actually we have the model files containing ESD effects. But whats the 
parameter we can look to tell,
whether it is passed/failed. Also test modes like PS,PD,NS,ND  
PALL,NALL,PDS,NDS  PC,NC tells how can we test after manufacturing.
But I need before silicon, how can we get the ESD performance for whole chip 
(I/O pads + Package effects), probably not CDM now, 
as core logic is under design phase.


From: Srivats Partha <vats123@xxxxxxxxx>

Hello ppl
I feel hspice wll not allow you to simulate the ESD compliance of a I/O pad.The 
reason being HSPICE will not simulate a MOSFET beyond the saturation region. 
Using HSPICE only the linear and saturation regions of a MOSFET can be 
simulated. But to verify the ESD complaince     MOSFET characteristics beyond 
saturation in break down and snap back needs to be studied. The lateral PNP BJT 
formed after the MOSFET breakdown needs to be studied. I am not sure if there 
is a method to study this unless yu do the simulations with a MOSFET and a PNP 
transistor connected. You may also have to model the  current source which 
depicts the Avalanche characteristics.  Thats how we are looking to study the 
ESD characteristics in our lab. I hope my explanation is on the right track.  
Else you might have to use simulators which study MOSFET behavior in the high 
current , voltage region. I wud very interested to know if there are other 
methods to do this.

From: Yafei Bi <yafei_bi@xxxxxxxxx>

if you have the device model for the ESD protection devices/network, then you 
can build the test benches for ESD event(HBM, CBM etc.), and simulate ESD 
event/compliance in HSpice. That will give you some idea on whether the I/O 
design can meet the ESD requirement or not.
If you don't have ESD device model, then you have to use T-CAD to generate the 
I-V characteristic 
of the protection devices. Hopely you can do the same experiment on the device 
see the difference.Eventually, ESD test on silicon is the final proof.

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