[SI-LIST] Re: Drive strength to Load conversion
- From: "Chen, Sherman" <sherman.chen@xxxxxxx>
- To: "tom@xxxxxxxxxxxxxxxxx" <tom@xxxxxxxxxxxxxxxxx>, "weirsi@xxxxxxxxxx" <weirsi@xxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 19 Aug 2014 00:59:02 +0000
Thanks, Tom.
By Rseries I mean the Thevenin resistance which includes the FET channel
resistance and the series resistor if exists. To pin point the behavior yes an
I/O curve will be needed.
Best Regards,
Sherman Chen
Signal Integrity
EMC Global Hardware Engineering
Tel: +86 21 60951100-3329
-----Original Message-----
From: Tom Dagostino [mailto:tom@xxxxxxxxxxxxxxxxx]
Sent: Tuesday, August 19, 2014 8:47 AM
To: Chen, Sherman; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Drive strength to Load conversion
Sherman
Yes, that is the implication. The equivalent output impedance could be much
lower.
But it is best to view this as what it is in most cases, a CMOS device that is
large enough to sink the spec's current and provide an "IR Drop" of less than
0.4V in this example. There are many drivers that have a built in series
resistance that will dominate the output current over the operating current
range and then you mostly have a true IR drop in the output. I've seen these
series resistor in series with the output and sometimes in series with just the
pulldown or pullup device. But most drivers have no internal series resistors
so the IV characteristics seen by the outside world is the DC characteristics
of the FET. At low Vds the output looks like a resistor and at higher Vds the
FET looks like a current source/sink.
A typical 8 mA driver may sink 10 to 30mA or higher at 0.4V.
Regards,
Tom Dagostino
Teraspeed Labs
9999 SW Wilshire Street
Suite 102
Portland, OR 97225
tom@xxxxxxxxxxxxxxxxx
www.teraspeedlabs.com
971-279-5325 office
503-430-1065 cell
-----Original Message-----
From: Chen, Sherman [mailto:sherman.chen@xxxxxxx]
Sent: Monday, August 18, 2014 5:11 PM
To: tom@xxxxxxxxxxxxxxxxx; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Drive strength to Load conversion
Tom,
If a device' spec claims its output remains below 0.4V when sinking 8mA, the
actually Vo could be way below 0.4V which mean a much smaller Rseries. And it's
the Rseries that determines the max sinking current - correct me if not the
case.
And you are right, normally high speed buffer spec don't give the output
current rating/capacitance, they just give output voltage/slew rate at test
load.
Best Regards,
Sherman Chen
Signal Integrity
EMC Global Hardware Engineering
Tel: +86 21 60951100-3329
-----Original Message-----
From: Tom Dagostino [mailto:tom@xxxxxxxxxxxxxxxxx]
Sent: Tuesday, August 19, 2014 5:23 AM
To: Chen, Sherman; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Drive strength to Load conversion
Be very careful looking at current specs of drivers. An 8mA driver is really
saying that at 0.4V the part will sink at least 8 mA. In all likely hood it
will sink much more than 8 mA at 0.4V and during the transition from high to
low (I'm only talking about the pulldown device for a typical CMOS driver here,
there is a similar set of specs for the pullup device) the device can sink much
more current, likely 100mA or more. Look at the IBIS model for the driver to
see its current capabilities.
I have never seen an output current spec with a capacitive load. Capacitive
load specs are only given for delays or if present rise and fall times. The
current specs of a driver are DC specs, not AC specs.
Tom Dagostino
Teraspeed Labs
9999 SW Wilshire Street
Suite 102
Portland, OR 97225
tom@xxxxxxxxxxxxxxxxx
www.teraspeedlabs.com
971-279-5325 office
503-430-1065 cell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Chen, Sherman
Sent: Monday, August 18, 2014 1:52 PM
To: weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Drive strength to Load conversion
While Steve explained the essentials of the matter from both low slew rate and
high slew rate scenarios, I think Ajay's question is about why in most spec the
output current is given with specified capacitive loads. For example, a HCSL
clock buffer gives the current capability of its output with the load condition
specified as a 100Ohm tline with two 2pf shunt caps to GND at the end on each
+/- line. And many lower freq. chips give their tr,tf spec. with the test load
as 10-50pF //1k resistor.
So Ajay,
For the low freq. case, the spec. of tr,tf are actually telling how much is the
output resistance which is the R value in the formula tr(10%-90%) = 2.2RC.
For the high freq. case (the HCSL one above), I guess this is the one you are
asking about, first with the cap load at the end of tline there will be some
ringing following each transition edge of the signal - if the signal rate is
not that fast so the charge/discharge of the cap can be finished soon after
each edge before next edge. The same Ohmic law is still the rule that
determines the voltage/current relationship here - even in high freq.
case. So using the RLC charging/discharging formula you can calculate the peak
current of the ringing which's rms value I think should be the output current
capacity in the spec. A simplified way of calculation is to use RC instead of
RLC with R replaced with Z which is the characteristic impd. of the tline. You
need to create a lattice diagram if doing the calculation manually.
Best Regards,
Sherman Chen
Signal Integrity
EMC Global Hardware Engineering
Tel: +86 21 60951100-3329
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of steve weir
Sent: Sunday, August 17, 2014 5:41 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Drive strength to Load conversion
If we take the rash assumption that your rise and fall times are so slow that
you can treat your traces as simple ohmic interconnects, then you can analyze
your timing like it was 1985. The rational disconnect here is that if your rise
and fall times are that slow, then why would you be concerned about skew from
capacitive loading? Do you have an enormous fan out?
If your rise and fall times are fast enough that the interconnects are
transmission lines, then if you have so much capacitance at the far end that
|Ztxline|*C >> [Trise, Tfall] then you have a reflection issues and
|Ztxline|failing
to control your interconnect impedance is going to make that even worse. If
your timing budget cannot handle capacitive charging at your loads, then it is
extremely unlikely that it will tolerate a number of round trip delays to
settle out. If any of the signals are clocks or timing strobes then you could
be walking into multiple transition nightmares.
I think that what you need to do is understand your signaling requirements
first. That will tell you how sloppy your timing can be and whether you need
to engineer as though it is the current or past century.
Steve.
On 8/16/2014 11:20 PM, Ajay Dhingra wrote:
> Hi Lee
> Thanks for your reply.
> I further have two things in my mind.
>
> First: I don't have a controlled impedance environment.
> Second: for any Transmission line, there is a cap load at the end of
> the transmission line. The cap load requires certain amount of charge
> so that it's voltage reaches logical threshold with a desired ramp. at
> the end of the day cap will change the ramp and hence timing. And
> eventual ramping of that voltage is determined by drive strength of
> the driver. though it happens in stages, first charging the
> transmission line and then transmission lines forwards the same ramp
> to cap load. So my question is how to approximate the drivers
> capability for a particular load or what max load a drive can drive
> based
upon its drive strength.
>
> Thanks
> Ajay
>
>
> On Sat, Aug 16, 2014 at 11:50 PM, Lee <leeritchey@xxxxxxxxxxxxx> wrote:
>
>> We don't drive capacitive loads any more. We drive impedances on the
>> order of 50 ohms. transmission lines.
>>
>>
>> -----Original Message----- From: Ajay Dhingra
>> Sent: Saturday, August 16, 2014 11:09 AM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: Drive strength to Load conversion
>>
>>
>>
>> Sent from my Huawei Mobile
>>
>> -------- Original Message --------
>> Subject: Re: [SI-LIST] Drive strength to Load conversion
>> From: Ajay Dhingra <ajay.dhingra@xxxxxxxxx>
>> To: Lee <leeritchey@xxxxxxxxxxxxx>
>> CC: si-list@xxxxxxxxxxxx
>>
>> Just for first order estimation if that particular drive strength is
>> sufficient for an equivalent cap load. Or in other words what max cap
>> load can be driven by x mA drive strength.
>>
>> in a situation when only drive strength in mA information is
>> available how to assess the driver capability.
>>
>> Thanks
>> Ajay
>>
>> Sent from my Huawei Mobile------------------------
>> ------------------------------------------
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>
--
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