[SI-LIST] Re: DDR3 termination on address / control lines
- From: "Bhagwath, Nitin" <Nitin_Bhagwath@xxxxxxxxxx>
- To: "joel@xxxxxxxxxx" <joel@xxxxxxxxxx>, SI-List <si-list@xxxxxxxxxxxxx>
- Date: Thu, 1 May 2014 05:50:19 +0000
Hello Joel,
If you're using Aria II GX (from your other question), if I recall correctly,
you don't have the option of fly-by since there's no leveling feature for that
controller.
Regards,
-Nitin
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Joel Brown
Sent: Wednesday, April 23, 2014 10:37 AM
To: SI-List
Subject: [SI-LIST] DDR3 termination on address / control lines
In my design there are two DDR3 chips on the boards.
Is it better to use a fly by termination or T with matched branches?
I am guessing fly by has better signal integrity and T has less skew between
the parts, Not sure with just parts if skew would be an issue.
I will be simulating this but wanted to see if there is preferred approach.
We were given a reference design that does use T termination but I don't think
it means we have to follow it.
Thanks
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