[SI-LIST] Re: DDR3 termination on address / control lines
- From: Rick Collins <gnuarm.2006@xxxxxxxxx>
- To: SI-List <si-list@xxxxxxxxxxxxx>
- Date: Wed, 23 Apr 2014 14:00:48 -0400
Both methods are a compromise of course. The fly by has a signal
propagating in both directions from the middle. I assume that would
mean it sees a lower impedance than the end chips. I can't imagine
how well that would work if they are parallel terminated. I guess
I've seen people do the fly by before, but only on slower signals
where there is time to settle which is not the case with memory
interfaces. How do you see this working?
The T circuit is also a compromise. I've only seen this analyzed
once by Dr. Johnson. I forget the significant details, but there is
a recognition that the trace impedance is not the same across the
T. I don't recall if it was bi-dir or not. I guess the data bus is
the hard part. I can't imagine what happens to data coming back from
the memory to the controller. That has got to be ugly.
With either method keeping your chips close together helps. Can you
put them on opposite sides of the board? That can make your stubs
very short. BTW, do you know your edge rates?
Rick
At 01:37 PM 4/23/2014, you wrote:
>In my design there are two DDR3 chips on the boards.
>Is it better to use a fly by termination or T with matched branches?
>I am guessing fly by has better signal integrity and T has less skew
>between the parts,
>Not sure with just parts if skew would be an issue.
>I will be simulating this but wanted to see if there is preferred approach.
>We were given a reference design that does use T termination but I don't
>think it means we have to follow it.
>Thanks
>
>
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