[SI-LIST] Re: DDR3 termination on address / control lines
- From: "Hany Fahmy" <hanymhfahmy@xxxxxxxxxxxxxxxxxxx>
- To: <joel@xxxxxxxxxx>, "'SI-List'" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 23 Apr 2014 19:58:24 +0200
I love Eric's answer "It depends": as I really depends on the Output-drive
strength and output-Slew-rate capability of the controller, I have to say
that MA/CMD & CNTL r very sensitive to Output-drive-strength & also
slre-rate, if it is only two sdrams then I vote for T-topology if I have
good control over the output-drive-strength and output-slew-rate to meet the
required timings especially of u target 1N mode. It also depends on which
speed-bin? I guess u want to shoot for 1600 or may be 1866?
U r correct in comparing both cases n use the best topology that meet ur
possible impedance targets & x-talk & return-path-discontinuity
requirements.
Highly recommend ref these signals to VDD n keep clock running w them on
same layer as possible to reduce the clock centering error.
Remember also to use the topology that will allow u to have similar clock
output-drive strength and slew-rate so that u also reduce the
CLK-2-MA/CMD/CNTL error budget @ controller side.
Hany Fahmy
CEO & Chief Consultant Officer
Intelligent Solutions BVBA
hanymhfahmy@xxxxxxxxxxxxxxxxxxx
http://www.intelligentsolutionsbvba.com/
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Joel Brown
Sent: Wednesday, April 23, 2014 7:37 PM
To: SI-List
Subject: [SI-LIST] DDR3 termination on address / control lines
In my design there are two DDR3 chips on the boards.
Is it better to use a fly by termination or T with matched branches?
I am guessing fly by has better signal integrity and T has less skew between
the parts, Not sure with just parts if skew would be an issue.
I will be simulating this but wanted to see if there is preferred approach.
We were given a reference design that does use T termination but I don't
think it means we have to follow it.
Thanks
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