[SI-LIST] Re: DDR3 controller internal package delay Considerlation
- From: pishang li <lipishang@xxxxxxxxx>
- To: "weirsi@xxxxxxxxxx" <weirsi@xxxxxxxxxx>
- Date: Sun, 2 Dec 2012 20:24:13 +0800
Hi Steve,
Thanks!Package desinger told me he did not know the model because this is
just a test chip.So I try to find some experience on this case.
ÔÚ 2012Äê12ÔÂ2ÈÕÐÇÆÚÈÕ£¬steve weir <weirsi@xxxxxxxxxx> дµÀ£º
> You more or less have four choices:
>
> Obtain a spec from the IC manufacturer,
> Obtain a model from the IC manufacturer,
> Generate a model from measurements,
> Guess
>
> Steve.
> On 12/2/2012 3:55 AM, pishang li wrote:
>> Hi,
>> Recently I have a case which is the DDR3 1600 layout consideration.I
found
>> our DDR3 Controller has about some skew on the same DQ lane.For example
>> DQ0 to DQ7 .The maxim trace length difference is about 200mil Cu trace
>> internal the Controller from Die to Pin.my question is that do I need
>> consider this skew made by package.If yes.How calculate this skew to meet
>> +-10mil on the PCB£¿Because I do not familiar with the package parameter
>> .Just know is Cu trace from Die to Pin/Pad.
>>
>>
>>
>>
>> Br
>> Shuang
>>
>>
>
>
> --
> Steve Weir
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--
Br,
pishang
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