[SI-LIST] Re: DDR3 controller internal package delay Considerlation
- From: jackle zheng <zheng.jackle@xxxxxxxxx>
- To: lipishang@xxxxxxxxx
- Date: Tue, 18 Dec 2012 14:28:20 +0800
hi,
as to the length of from die to package ball, you can get from the
substrate design company. most company have the work outsource to substrate
design company.
in fact, you don't need to care too much about the skew. DDR controller
side have many ways to eliminate skew between DQs line at anyone byte
lane.even the skew between DQS line and CK. for example, change the delay
time of each BDL etc. you just try to minimize the board level skew at
+-100mil.
2012/12/3 pishang li <lipishang@xxxxxxxxx>
> Hi Steve,
> Thanks!Package desinger told me he did not know the model because this is
> just a test chip.So I try to find some experience on this case.
>
> ÔÚ 2012Äê12ÔÂ2ÈÕÐÇÆÚÈÕ£¬steve weir <weirsi@xxxxxxxxxx> дµÀ£º
> > You more or less have four choices:
> >
> > Obtain a spec from the IC manufacturer,
> > Obtain a model from the IC manufacturer,
> > Generate a model from measurements,
> > Guess
> >
> > Steve.
> > On 12/2/2012 3:55 AM, pishang li wrote:
> >> Hi,
> >> Recently I have a case which is the DDR3 1600 layout consideration.I
> found
> >> our DDR3 Controller has about some skew on the same DQ lane.For example
> >> DQ0 to DQ7 .The maxim trace length difference is about 200mil Cu trace
> >> internal the Controller from Die to Pin.my question is that do I need
> >> consider this skew made by package.If yes.How calculate this skew to
> meet
> >> +-10mil on the PCB£¿Because I do not familiar with the package parameter
> >> .Just know is Cu trace from Die to Pin/Pad.
> >>
> >>
> >>
> >>
> >> Br
> >> Shuang
> >>
> >>
> >
> >
> > --
> > Steve Weir
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> --
> Br,
> pishang
>
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