[SI-LIST] Re: DDR2 Clock and DQS Lines
- From: "Dhavale Bipin-abd026" <bipinpd@xxxxxxxxxxxx>
- To: <kenny_frohlich@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 27 Dec 2006 12:52:56 +0800
DQS needs to be matched to CLKs.
To what extent you need to length match depends on the tDQSS of the
controller and the DDR DRAM.
In the JEDEC spec for DDR SDRAM, its specified as 0.75-1.25 * tCK or +/-
0.25 tCK deviation from the norm[1 tCK].
i.e after a write command the data strobe *must* transition in 0.75-1.25
* tCK.
For controllers its usually +/-0.06 to +/-0.1 tCK. [Check the controller
datasheet].
So the maximum allowable skew would be 0.25 tCK - 0.1 tCK =3D 0.15 tCK.
If operating at high frequencies, its good to match the whole data group
[all 72 bits]=20
within 1.5 inches[or even tighter] and route the clocks somewhere in
between.
Regards,
Bipin
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Kenny Frohlich
Sent: Wednesday, December 27, 2006 9:27 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR2 Clock and DQS Lines
Hi All,
I understand that DQ and DQM lines need to match length with DQS
lines, and Addr/Control lines need to length match with clocks. But do
DQS lines need to length match with clocks?
In AMD design guidelines, they specifies that DQS lines need to length
match with DDR2 clocks. But is this really a requirement (industry
standard)?
=20
Thanks,
Kenny
=20
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