[SI-LIST] Re: DDR2 Clock and DQS Lines
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: <kalevi@xxxxxxxxxx>, <kenny_frohlich@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 1 Jan 2007 17:52:00 -0800
Kenny,
The length matching rules for DDR2 interfaces can be broken into
multiple levels. The most stringent rules are for DQ and DM to DQS=20
strobe, within a byte lane. This is the most critical timing path. Here
you need to match all signals within the byte lane to within a fairly
tight
range, and all signals within a byte lane should be routed on the same
layer.
While length matching to CLK is also required, these rules are generally
not as
stringent as data to strobe. For example, you might have a 1" length
window
around CLK length, in which to route CTRL or ADR/CMD signals. There is
also a
length window for all strobes with respect to CLK.
In the designs I have participated in these length windows are wide
enough to
allow the CTRL, ADR/CMD, and DQS signals to be routed without excessive
length tuning.
Its the byte lanes that require most of the tuning. Then the CLKs need
to be adjusted
in length so as to get the length windows aligned to the natural routing
lengths of CTRL,=20
ADR/CMD, and DQS. Of course every case is different. Where you can run
into trouble
is if you have non-standard placements where the controller and the
memory connectors
are not placed symetrically. This can create a fairly wide length
variance across the=20
connector and make length matching extremely difficult.=20
Consult the design guidelines for the controller you are using for more
details on the
width of the length matching windows for different signal groups. =20
Brian P. Moran
Intel Corporation=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Kai Keskinen
Sent: Saturday, December 30, 2006 5:42 PM
To: kenny_frohlich@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR2 Clock and DQS Lines
Kenny:
Read any app note from anyone that makes a DDR or DDR2 controller. Your
AMD app note is telling you the right way to implement your interface if
you want it to work. The strobe has to have some tolerance to the clock
and then the data bits corresponding to that strobe have to have even
tighter tolerance to the strobe. This forms a byte lane. You can also
check out the DDR or DDR2 JEDEC specs at the JEDEC site for more
details. Micron has a wealth of application notes too.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Kenny Frohlich
Sent: Tuesday, December 26, 2006 10:57 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR2 Clock and DQS Lines
Hi All,
I understand that DQ and DQM lines need to match length with DQS
lines, and Addr/Control lines need to length match with clocks. But do
DQS lines need to length match with clocks?
In AMD design guidelines, they specifies that DQS lines need to length
match with DDR2 clocks. But is this really a requirement (industry
standard)?
Thanks,
Kenny
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