[SI-LIST] Re: DDR2 Clock and DQS Lines
- From: "Peterson, James F \(EHCOE\)" <james.f.peterson@xxxxxxxxxxxxx>
- To: <kenny_frohlich@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 28 Dec 2006 17:06:11 -0600
Kenny,
yes it needs to be matched......now anticipating that your next question
is : "but why??" (which I would certainly also ask): The reason is that
the DQ info that just was clock into the memory with DQS must now cross
into the SDRAM's internal local clock domain, which is based on CK and
CKn, and you can't cross clock domains, without establishing a
relationship between the clocks (DQS and CK)...(that is, unless you want
to drop bits - and if you just double-register you will drop bits.)
take care.
Jim Peterson
Honeywell=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Kenny Frohlich
Sent: Tuesday, December 26, 2006 10:57 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR2 Clock and DQS Lines
Hi All,
I understand that DQ and DQM lines need to match length with DQS
lines, and Addr/Control lines need to length match with clocks. But do
DQS lines need to length match with clocks?
In AMD design guidelines, they specifies that DQS lines need to length
match with DDR2 clocks. But is this really a requirement (industry
standard)?
=20
Thanks,
Kenny
=20
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