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- » [SI-LIST] Re: DDR2 IMPEDANCE -
- » [SI-LIST] Re: DDR2 IMPEDANCE -
- » [SI-LIST] Re: trace length matching -
- » [SI-LIST] Product engineer position at PLX -
- » [SI-LIST] Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Measuring signals in the presence of significant noise - part 2 -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Re: DDR2 IMPEDANCE -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Re: DDR2 IMPEDANCE -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Re: DDR2 IMPEDANCE -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] IBIS Model -
- » [SI-LIST] About S2ibis3 -
- » [SI-LIST] Re: IBIS Model -
- » [SI-LIST] Re: About S2ibis3 -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] IPC/DC Boston mtg, 13-Dec -
- » [SI-LIST] Fab capabilities -
- » [SI-LIST] HSPICE Fieldsolver vs FastHenry -
- » [SI-LIST] Re: HSPICE Fieldsolver vs FastHenry -
- » [SI-LIST] Re: HSPICE Fieldsolver vs FastHenry -
- » [SI-LIST] Re: HSPICE Fieldsolver vs FastHenry -
- » [SI-LIST] Re: Spectre S-parameter based modeling- Stability issues -
- » [SI-LIST] Re: Fab capabilities -
- » [SI-LIST] Re: HSPICE Fieldsolver vs FastHenry -
- » [SI-LIST] Re: Fab capabilities -
- » [SI-LIST] Re: HSPICE Fieldsolver vs FastHenry -
- » [SI-LIST] Re: HSPICE Fieldsolver vs FastHenry -
- » [SI-LIST] Re: HSPICE Fieldsolver vs FastHenry -
- » [SI-LIST] Re: HSPICE Fieldsolver vs FastHenry -
- » [SI-LIST] CST vs. HFSS -
- » [SI-LIST] Re: Update on Pulse Research Lab 12 GHz clock divider sample -
- » [SI-LIST] Re: DDR2 IMPEDANCE -
- » [SI-LIST] SI related jobs at Mobilygen; -
- » [SI-LIST] December 2006 IEEE EMC Silicon Valley Chapter meeting. Topic: Incorporate RoHS and WEEE in to production design -
- » [SI-LIST] December 2006 IEEE EMC Silicon Valley Chapter meeting. Topic: Incorporate RoHS and WEEE in to production design -
- » [SI-LIST] Free Oscilloscope Tools Software -
- » [SI-LIST] Free Oscilloscope Tools Software -
- » [SI-LIST] SI Tool Justification Document -
- » [SI-LIST] ROOKIE: Anti-Pad Size Effect On Signal Integrity -
- » [SI-LIST] High speed board design project (6-9 months) in Bay Area, CA -
- » [SI-LIST] Re: ROOKIE: Anti-Pad Size Effect On Signal Integrity -
- » [SI-LIST] Re: ROOKIE: Anti-Pad Size Effect On Signal Integrity:By the formula, as F goes up, Xc goes down (was up by typo) -
- » [SI-LIST] Re: SI Tool Justification Document -
- » [SI-LIST] Re: SI Tool Justification Document -
- » [SI-LIST] Re: SI Tool Justification Document -
- » [SI-LIST] Re: ROOKIE: Anti-Pad Size Effect On Signal Integrity -
- » [SI-LIST] CPLD Device Failures... -
- » [SI-LIST] Re: ROOKIE: Anti-Pad Size Effect On Signal Integrity:By the formula, as F goes up, Xc goes down (was up by typo) -
- » [SI-LIST] Re: ROOKIE: Anti-Pad Size Effect On Signal Integrity:By the formula, as F goes up, Xc goes down (was up by typo) -
- » [SI-LIST] Re: ROOKIE: Anti-Pad Size Effect On Signal Integrity -
- » [SI-LIST] Insertion Loss of Passive Components -
- » [SI-LIST] Insertion Loss of Passive Components -
- » [SI-LIST] Re: SI Tool Justification Document -
- » [SI-LIST] Re: ROOKIE: Anti-Pad Size Effect On Signal Integrity: By the formula, as F goes up, Xc goes down (was up by typo) -
- » [SI-LIST] Re: ROOKIE: Anti-Pad Size Effect On Signal Integrity: By the formula, as F goes up, Xc goes down (was up by typo) -
- » [SI-LIST] Re: ROOKIE: Anti-Pad Size Effect On Signal Integrity: By the formula, as F goes up, Xc goes down (was up by typo) -
- » [SI-LIST] Reg: USB OTG Controller -
- » [SI-LIST] Re: Insertion Loss of Passive Components -
- » [SI-LIST] Re: Insertion Loss of Passive Components -
- » [SI-LIST] Variable Freq generator for Circuit/Schematic Testbenching -
- » [SI-LIST] Re: Insertion Loss of Passive Components -
- » [SI-LIST] Re: Insertion Loss of Passive Components -
- » [SI-LIST] Re: Variable Freq generator for Circuit/Schematic Testbenching -
- » [SI-LIST] Re: Variable Freq generator for Circuit/Schematic Testbenching -
- » [SI-LIST] Re: Variable Freq generator for Circuit/Schematic Testbenching -
- » [SI-LIST] 3 month project in Milpitas, CA (ONSITE) -
- » [SI-LIST] Test -
- » [SI-LIST] Looking for Signal Integrity Trainer Kits -
- » [SI-LIST] Decoupling Strategy?? -
- » [SI-LIST] Re: Decoupling Strategy?? -
- » [SI-LIST] Job opening: Senior EMI/EMC Engineer -
- » [SI-LIST] Re: 3 month project in Milpitas, CA (ONSITE) -
- » [SI-LIST] Re: Looking for Signal Integrity Trainer Kits -
- » [SI-LIST] Eye Diagram Viewing Tool -
- » [SI-LIST] Eye Diagram comparison -
- » [SI-LIST] Re: Insertion Loss of Passive Components -
- » [SI-LIST] Re: Insertion Loss of Passive Components -
- » [SI-LIST] Re: Insertion Loss of Passive Components -
- » [SI-LIST] Re: CST vs. HFSS -
- » [SI-LIST] Re: CST vs. HFSS -
- » [SI-LIST] Re: CST vs. HFSS -
- » [SI-LIST] Re: Insertion Loss of Passive Components -
- » [SI-LIST] Inductors -
- » [SI-LIST] Re: Inductors -
- » [SI-LIST] Re: Eye Diagram Viewing Tool -
- » [SI-LIST] Re: Looking for Signal Integrity Trainer Kits -
- » [SI-LIST] Validating IBIS Models -
- » [SI-LIST] Re: Test -
- » [SI-LIST] Transmission line impedance -
- » [SI-LIST] R: Transmission line impedance -
- » [SI-LIST] DDR2 AND DDR3 -
- » [SI-LIST] Re: Transmission line impedance -
- » [SI-LIST] Re: R: Transmission line impedance -
- » [SI-LIST] Re: Transmission line impedance -
- » [SI-LIST] Re: Transmission line impedance -
- » [SI-LIST] Re: Transmission line impedance -
- » [SI-LIST] which vendors have good ibis/spice models for 4-rank ddr2 rdimm register ? -
- » [SI-LIST] Why 50 ohms? The history. -
- » [SI-LIST] Re: Why 50 ohms? The history. -
- » [SI-LIST] Re: Out of Office AutoReply: which vendors have good ibis/spice models for 4-rank ddr2 rdimm register ? -
- » [SI-LIST] Re: which vendors have good ibis/spice models for 4-rank ddr2 rdimm register ? -
- » [SI-LIST] Re: Why 50 ohms? The history. -
- » [SI-LIST] ibis -
- » [SI-LIST] Re: ibis -
- » [SI-LIST] Re: ibis -
- » [SI-LIST] Re: ibis -
- » [SI-LIST] Re: ibis -
- » [SI-LIST] Re: ibis -
- » [SI-LIST] Re: ibis -
- » [SI-LIST] Differential traces over a split in the ground plane -
- » [SI-LIST] Re: Differential traces over a split in the ground plane -
- » [SI-LIST] Re: IBIS Model -
- » [SI-LIST] R: Differential traces over a split in the ground plane -
- » [SI-LIST] Re: ibis -
- » [SI-LIST] Re: ibis -
- » [SI-LIST] Re: ibis -
- » [SI-LIST] Calling libraries in Hspice -
- » [SI-LIST] Re: Decoupling Strategy?? -
- » [SI-LIST] ESD Symposium interviews -
- » [SI-LIST] DDR2 Clock and DQS Lines -
- » [SI-LIST] Re: DDR2 Clock and DQS Lines -
- » [SI-LIST] Re: DDR2 Clock and DQS Lines -
- » [SI-LIST] DDR3 SODIMM Module -
- » [SI-LIST] Stimulus for spice-to-IBIS -
- » [SI-LIST] Re: Decoupling Strategy?? -
- » [SI-LIST] How to setup SI team, how to be SI team manager and how to make SI project plan? -
- » [SI-LIST] Hspice simulation is too slow -
- » [SI-LIST] Re: DDR2 Clock and DQS Lines -
- » [SI-LIST] Re: How to setup SI team, how to be SI team manager and how to make SI project plan? -
- » [SI-LIST] Arm development platform - may be off from SI topics -
- » [SI-LIST] Re: Stimulus for spice-to-IBIS -
- » [SI-LIST] Re: Calling libraries in Hspice -
- » [SI-LIST] SiP Conference in San Jose, Jan 23 and 24, 2007 -
- » [SI-LIST] Re: DDR2 Clock and DQS Lines -
- » [SI-LIST] Re: DDR2 Clock and DQS Lines -