[SI-LIST] Re: Bypass Capacitor Selection
- From: steve weir <weirsp@xxxxxxxxxx>
- To: Vinu Arumugham <vinu@xxxxxxxxx>, leeritchey@xxxxxxxxxxxxx
- Date: Fri, 02 Jan 2004 16:43:39 -0800
Vinu, I am talking about X2Y's, the four terminal parts licensed by X2Y
Corp. that consist of 2 interdigitated multilayer Y capacitors. They have
an A, B, and G1, and G2 terminals. The G1 and G2 terminals oppose on the
short axis of the parts, and are typically soldered to one contiguous land
with three vias. Each the A and B terminals are also typically mounted
with 2 to three vias each, because mounting inductance is the limiting
performance factor.
Before mounting, these parts have demonstrated ESL's under 100pH, ( Phycomp
has measured under 50pH ) and do not suffer inductance proportional to
package size. They are an entirely different ball game than traditional
MLC, or MLC arrays. The arithmetic is a comparison of 1/(Ls + Lm). The
correct conclusions reached by Lee, Mike Greim and others about reverse
geometry caps is due to the fact that Ls is still large enough with reverse
geometry parts that the overall value is not much improved. However, with
X2Ys, Ls is an order of magnitude lower using LARGER packages, such as
0805, or even 1206 that afford means to drop Lm by way of multiple vias per
pad.
If we were to take X2Y's and use only a single via per pad, then Lm would
be on the order of 1nH. While that would still be a significant
improvement over ordinary or reverse geometry caps, there would be little
cost or area improvement. However, when we drill 3 vias per pad, Lm drops
commensurately, and because Ls is so small, Lm completely dominates. Our
HF ( > 10MHz ) impedance becomes mostly function of via hole count, and we
get the benefit that we can cluster those holes around far fewer
parts. So, even though the caps are about 2X price, we still save in raw
component cost, drilled hole count, and assembly cost. In some cases we
can meet target impedance within a package density that would otherwise not
be attainable.
Steve.
At 04:12 PM 1/2/2004 -0800, Vinu Arumugham wrote:
>Steve is talking about X2Y devices but Lee's responses seem to be
>referring to array capacitors.
>
>If I understand correctly, X2Y is not an array capacitor. Are you both
>referring to the same part or am I missing something?
>
>Thanks,
>Vinu
>
>Lee Ritchey wrote:
>>
>>Steve,
>>
>>I agree with all of the reasoning on how much lower the inductance gets
>>with each option. What counts is the overall effect on impedance vs.
>>frequency. That's the final test. When these tests are made, lowering the
>>inductance shifts the series resonant frequency higher, but by how much.
>>Again, the measured data shows not enough to warrant the extra cost.
>>
>>Lee
>>
>>
>>
>>>
>>>[Original Message]
>>>From: steve weir <mailto:weirsp@xxxxxxxxxx><weirsp@xxxxxxxxxx>
>>>To: <mailto:leeritchey@xxxxxxxxxxxxx><leeritchey@xxxxxxxxxxxxx>; David
>>>Anthony <mailto:x2y@xxxxxxx><x2y@xxxxxxx>;
>>>
>>
>><mailto:jmartinson@xxxxxxxxxxxxxxxxx><jmartinson@xxxxxxxxxxxxxxxxx>;
>><mailto:si-list@xxxxxxxxxxxxx><si-list@xxxxxxxxxxxxx>;
>><mailto:si-list@xxxxxxxxxxxxx><si-list@xxxxxxxxxxxxx>
>>
>>>
>>>Date: 1/2/2004 2:57:33 PM
>>>Subject: Re: [SI-LIST] Re: Bypass Capacitor Selection
>>>
>>>Lee, I appreciate the problem. First, I think that we can agree on
>>>
>>
>>taking
>>
>>>
>>>a graphical evaluation of the data. Since we are inductance limited, the
>>>total mounted inductance of a given decoupling element will determine its
>>>high frequency effectiveness.
>>>
>>>By using multiple vias with a single cap, generally total impedance
>>>
>>
>>results
>>
>>>
>>>are better than using the same area to put in more capacitors. With
>>>
>>
>>three
>>
>>>
>>>vias per pad, for each: the A, B, and G1/G2 pads inductances as low as
>>>300pH can be met for a single cap for the mounting structure.
>>>
>>>Now, if we use a typical 0603 with 800-1000pH, the best that we can get
>>>
>>
>>is
>>
>>>
>>>1100 - 1300pH. With a reverse geometry capacitor we can get down to
>>>
>>
>>about
>>
>>>
>>>700pH which is better, but probably not worth the trouble. But if we use
>>>an X2Y that exhibits on the order of 100 pH, we drop down to about 400pH
>>>mounted. Now, our multiple vias really pay-off, as we are at about 1/3
>>>
>>
>>the
>>
>>>
>>>mounted inductance of a traditional geometry capacitor. For a given
>>>impedance target, we can use 1/3 the number of X2Y's as traditional caps,
>>>and a whole lot fewer total vias.
>>>
>>>Steve.
>>>
>>>At 02:44 PM 1/2/2004 -0800, Lee Ritchey wrote:
>>>
>>>>
>>>>Steve,
>>>>
>>>>As i mentioned, we measured all sorts of land patterns and their effect
>>>>
>>
>>on
>>
>>>>
>>>>the impedance vs. frequency that one sees on a PCB power supply. Figure
>>>>34.10 shows this with an array capacitor, 2 each 0603 capacitors with for
>>>>vias and an 0612 with twelve vias.
>>>>
>>>> >From this data, it can be seen that the array capacitor is only
>>>>
>>
>>marginally
>>
>>>>
>>>>better than a pair of 0603 capacitors at a much higher overall cost.
>>>>
>>>>To get real value from these very low inductance capacitors it is
>>>>
>>
>>necessary
>>
>>>>
>>>>to make a significant reduction in mounting inductance. That can happen
>>>>
>>
>>on
>>
>>>>
>>>>very thin substrates, such as BGA packages.
>>>>
>>>>The rest of the time, sticking with standard components is a good
>>>>compromise between performance and cost.
>>>>
>>>>I'm sure this news will not be appreciated by those making the array
>>>>
>>
>>style
>>
>>>>
>>>>capacitors, but that's how the measurements work out , but that's why we
>>>>made all of the measurements. We needed to know just what we were going
>>>>
>>
>>to
>>
>>>>
>>>>get from the various types of parts.
>>>>
>>>>Lee
>>>>
>>>>
>>>>
>>>>>
>>>>>[Original Message]
>>>>>From: steve weir <mailto:weirsp@xxxxxxxxxx><weirsp@xxxxxxxxxx>
>>>>>To: <mailto:leeritchey@xxxxxxxxxxxxx><leeritchey@xxxxxxxxxxxxx>; David
>>>>>Anthony <mailto:x2y@xxxxxxx><x2y@xxxxxxx>;
>>>>>
>>>>
>>>><mailto:jmartinson@xxxxxxxxxxxxxxxxx><jmartinson@xxxxxxxxxxxxxxxxx>;
>>>><mailto:si-list@xxxxxxxxxxxxx><si-list@xxxxxxxxxxxxx>;
>>>><mailto:si-list@xxxxxxxxxxxxx><si-list@xxxxxxxxxxxxx>
>>>>
>>>>>
>>>>>Date: 1/2/2004 9:17:45 AM
>>>>>Subject: Re: [SI-LIST] Re: Bypass Capacitor Selection
>>>>>
>>>>>Lee,
>>>>>
>>>>>I have become a big believer in the X2Y parts over the past several
>>>>>years. While, the land patterns naturally suit themselves to multiple
>>>>>
>>>>
>>>>vias
>>>>
>>>>>
>>>>>to mitigate the effects of attachment inductance, the presence of the
>>>>>
>>>>
>>>>G1/G2
>>>>
>>>>>
>>>>>plates make these devices perform much better than anything else I
>>>>>
>>
>>have
>>
>>>>>
>>>>>seen, ( as well as offering some applications regular caps can't do at
>>>>>
>>>>
>>>>all
>>>>
>>>>>
>>>>>). I love these things for SMPS and decoupling. The limited sources
>>>>>
>>
>>of
>>
>>>>>
>>>>>supply used to make them costly and hard to get, but that has improved
>>>>>quite a bit in the past 24 months, to the point where they are both
>>>>>performance and cost effective.
>>>>>
>>>>>One of the really amazing characteristics of these devices is the very
>>>>>
>>>>
>>>>well
>>>>
>>>>>
>>>>>behaved and lower impedance floor. Since we are limited largely by
>>>>>
>>
>>how
>>
>>>>>
>>>>>many vias we attach with, these devices are about as close to ideal
>>>>>
>>
>>as we
>>
>>>>>
>>>>>can get. I think it would be well worth your while to reevaluate
>>>>>decoupling to any particular target impedance using X2Ys versus any
>>>>>alternative. I believe you will be very pleasantly surprised.
>>>>>
>>>>>Steve.
>>>>>
>>>>>
>>>>>At 08:40 AM 1/2/2004 -0800, Lee Ritchey wrote:
>>>>>
>>>>>>
>>>>>>This is a good subject to explore. However, focusing on the
>>>>>>
>>
>>parasitic
>>
>>>>>>
>>>>>>inductance of the capacitor itself is too narrow a view. What
>>>>>>
>>
>>counts is
>>
>>>>>>
>>>>>>the total inductance, including the mounting pads and vias. On
>>>>>>
>>>>
>>>>multilayer
>>>>
>>>>>>
>>>>>>PCBs, the mounting inductance dominates the picture. When this had
>>>>>>
>>
>>been
>>
>>>>>>
>>>>>>taken into account, the ultralow inductance capacitors turn out to
>>>>>>
>>
>>be not
>>
>>>>>>
>>>>>>much better than the standard two terminal devices.
>>>>>>
>>>>>>While I haven't published any papers specifically on this topic, nor
>>>>>>
>>>>
>>>>have I
>>>>
>>>>>>
>>>>>>seen anyone else do so, we did treat this topic in great detail with
>>>>>>
>>
>>many
>>
>>>>>>
>>>>>>lab measurements in the book I published late last year. Don't mean
>>>>>>
>>
>>to
>>
>>>>>>
>>>>>>push the book in this reply, but want to make sure the information is
>>>>>>visible to those who are curious.
>>>>>>
>>>>>>On my web site, there is a list of articles, one by Micheal Grime
>>>>>>
>>
>>and one
>>
>>>>>>
>>>>>>by the engineers at UMR which sheds some light on the overall topic
>>>>>>
>>
>>of
>>
>>>>>>
>>>>>>capacitor selection. site is
>>>>>><http://www.speedingedge.com>www.speedingedge.com
>>>>>>
>>>>>>
>>>>>>Lee
>>>>>>
>>>>>>
>>>>>>
>>>>>>>
>>>>>>>[Original Message]
>>>>>>>From: David Anthony <mailto:x2y@xxxxxxx><x2y@xxxxxxx>
>>>>>>>To:
>>>>>>><mailto:jmartinson@xxxxxxxxxxxxxxxxx><jmartinson@xxxxxxxxxxxxxxxxx>;
>>>>>>><mailto:si-list@xxxxxxxxxxxxx><si-list@xxxxxxxxxxxxx>;
>>>>>>>
>>>>>>
>>>>>><mailto:si-list@xxxxxxxxxxxxx><si-list@xxxxxxxxxxxxx>
>>>>>>
>>>>>>>
>>>>>>>Date: 12/30/2003 2:27:02 PM
>>>>>>>Subject: [SI-LIST] Re: Bypass Capacitor Selection
>>>>>>>
>>>>>>>Jerry,
>>>>>>>
>>>>>>>Here are links to comparisons of standard discretes (also reverse
>>>>>>>
>>>>
>>>>aspect
>>>>
>>>>>>>
>>>>>>>caps) vs. an X2Y cap. The 4-terminal X2Y's internal design
>>>>>>>
>>
>>promotes
>>
>>>>>>>
>>>>>>>cancellation of mutual inductance. There have been discussions on
>>>>>>>
>>
>>the
>>
>>>>
>>>>list
>>>>
>>>>>>>
>>>>>>>as to what's the best test board for comparing vendor components
>>>>>>>
>>
>>and
>>
>>>>
>>>>we
>>>>
>>>>>>
>>>>>>look
>>>>>>
>>>>>>>
>>>>>>>forward to a standard emerging. We choose a PCB similar to one
>>>>>>>
>>
>>used
>>
>>>>
>>>>by UMR
>>>>
>>>>>>>
>>>>>>>in a paper they presented at the 2002 EMC Symposium. Bart Bouma of
>>>>>>>Yageo/Phycomp also compared X2Y to standard discretes on a similar
>>>>>>>
>>>>
>>>>board.
>>>>
>>>>>>>
>>>>>>>Links to data (watch for URL wrap):
>>>>>>>
>>>>>>>(1) X2Y vs.(5)different valued discretes(same size caps):
>>>>>>>
>>>>>>>
>>>
>>><http://www.x2y.com/cube/x2y.nsf/(files>http://www.x2y.com/cube/x2y.nsf/(files)/X2YPCB121203.pdf/$FILE/X2YPCB121203
>>>
>>>>
>>>>.
>>>>
>>>>>>>
>>>>>>>pdf
>>>>>>>
>>>>>>>
>>>>>>>Phycomp data: X2Y vs. standard discretes and low L reverse aspect
>>>>>>>
>>
>>caps
>>
>>>>>>>
>>>>>>>(0306):
>>>>>>>
>>>>>>>
>>>
>>><http://www.x2y.com/cube/x2y.nsf/(files>http://www.x2y.com/cube/x2y.nsf/(files)/092703X2YReverse.pdf/$FILE/092703X2
>>>
>>>>
>>>>Y
>>>>
>>>>>>>
>>>>>>>Reverse.pdf
>>>>>>>
>>>>>>>regards,
>>>>>>>Dave
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>-----Original Message-----
>>>>>>>From: <mailto:si-list-bounce@xxxxxxxxxxxxx>si-list-bounce@xxxxxxxxxxxxx
>>>>>>>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Jerry Martinson
>>>>>>>Sent: Tuesday, December 30, 2003 2:18 PM
>>>>>>>To: <mailto:si-list@xxxxxxxxxxxxx>si-list@xxxxxxxxxxxxx;
>>>>>>><mailto:si-list@xxxxxxxxxxxxx>si-list@xxxxxxxxxxxxx
>>>>>>>Subject: [SI-LIST] Re: Bypass Capacitor Selection
>>>>>>>
>>>>>>>
>>>>>>>Martin,
>>>>>>>
>>>>>>>To address your 3rd question, I'm a bit of a maverick as I believe
>>>>>>>
>>>>
>>>>that
>>>>
>>>>>>>
>>>>>>>using surface mount capacitor arrays are an often-overlooked
>>>>>>>
>>
>>trick for
>>
>>>>>>>
>>>>>>>having better decoupling performance at a reasonable cost. With
>>>>>>>
>>
>>most
>>
>>>>>>>
>>>>>>>designs, the via inductance is a large part of the impedance, cap
>>>>>>>inductance is also a larger but smaller component. To reduce
>>>>>>>
>>
>>this, it
>>
>>>>>>>
>>>>>>>makes sense to try to cram the vias for the two voltages close
>>>>>>>
>>>>
>>>>together
>>>>
>>>>>>>
>>>>>>>and it also makes sense to try to have more vias and caps in
>>>>>>>
>>
>>parallel.
>>
>>>>>>>
>>>>>>>There are limits to how much of this you can achieve for DFM,
>>>>>>>
>>
>>routing,
>>
>>>>>>>
>>>>>>>cost, and other reasons.
>>>>>>>
>>>>>>>For DFM reasons, you'll likely need to space your 0402 and 0603
>>>>>>>components further apart from each other than you'd ideally like.
>>>>>>>
>>>>
>>>>This
>>>>
>>>>>>>
>>>>>>>will limit your cap and via density. You'll also have some DFM
>>>>>>>resistance to putting the vias as close together and as close to
>>>>>>>
>>
>>the
>>
>>>>
>>>>SMT
>>>>
>>>>>>>
>>>>>>>pads as you'd ideally like. Cap arrays can partially solve these
>>>>>>>problems. Here are some points about using the cap arrays:
>>>>>>>
>>>>>>>1. They effectively put 4 0402 or smaller parts in the same area
>>>>>>>
>>
>>as
>>
>>>>
>>>>an
>>>>
>>>>>>>
>>>>>>>1206 or smaller. This means you can get a higher number of caps
>>>>>>>
>>
>>and
>>
>>>>>>>
>>>>>>>vias in a given area. =20
>>>>>>>2. Interdigitate so that much of the inductance works for you
>>>>>>>
>>
>>instead
>>
>>>>>>>
>>>>>>>of against you. Alternate power and ground so that the power
>>>>>>>
>>
>>isn't
>>
>>>>
>>>>all
>>>>
>>>>>>>
>>>>>>>on one side and the ground is on the other. There is a paper
>>>>>>>
>>
>>from AVX
>>
>>>>>>>
>>>>>>>on using expensive IDC cap arrays that show this. I think the
>>>>>>>
>>
>>IDC cap
>>
>>>>>>>
>>>>>>>arrays are nice but expensive. Using regular cap arrays on pads
>>>>>>>designed for the AVX IDC cap arrays, you can get the beneficial
>>>>>>>interdigitated mutual inductance in your vias, which are the
>>>>>>>
>>
>>larger
>>
>>>>
>>>>part
>>>>
>>>>>>>
>>>>>>>of the inductance. Another benefit of this is that if your
>>>>>>>
>>
>>decoupling
>>
>>>>>>>
>>>>>>>is found to be inadequate after your boards are made, you can use
>>>>>>>
>>>>
>>>>these
>>>>
>>>>>>>
>>>>>>>AVX IDC cap arrays without spinning your board.
>>>>>>>3. You may not be able to have the vias for the two voltages
>>>>>>>
>>
>>point
>>
>>>>>>>
>>>>>>>inward from the pads like you might have been able to with
>>>>>>>
>>
>>discretes.
>>
>>>>>>>
>>>>>>>So you'll have to look at your board's DFM rules. This may be a
>>>>>>>disadvantage of using the cap arrays.
>>>>>>>4. The purchase cost of the cap arrays is higher than 4
>>>>>>>
>>
>>discretes.
>>
>>>>>>>
>>>>>>>Average placement, etc... costs for each discrete are usually a
>>>>>>>
>>
>>couple
>>
>>>>>>>
>>>>>>>US cents. These costs per discrete always exist but may not be
>>>>>>>internalized in the assembly pricing you see. You'll have to
>>>>>>>
>>
>>look at
>>
>>>>>>>
>>>>>>>the economic ramifications of this. The situations I've seen
>>>>>>>
>>
>>slightly
>>
>>>>>>>
>>>>>>>favor an array versus four discretes so you can actually _SAVE_
>>>>>>>
>>
>>money
>>
>>>>>>>
>>>>>>>and have better decoupling.
>>>>>>>5. You can only use one value for the four elements in an array.
>>>>>>>
>>>>
>>>>This
>>>>
>>>>>>>
>>>>>>>may conflict with your other decoupling goals.
>>>>>>>6. You can't spread an array around like you can with discretes.
>>>>>>>
>>>>>>>I must caution you that I have not been able to do very good
>>>>>>>quantitative measurements comparing the cap array trick's
>>>>>>>
>>>>
>>>>effectiveness
>>>>
>>>>>>>
>>>>>>>versus the discrete caps effectiveness in perfect apples to apples
>>>>>>>tests. However based on the differences I've seen in similar
>>>>>>>
>>
>>boards
>>
>>>>>>>
>>>>>>>where I used discretes on one and arrays on another, I'm pretty
>>>>>>>
>>
>>sure
>>
>>>>>>>
>>>>>>>that using cap arrays has given me substantially less noise. So
>>>>>>>
>>
>>using
>>
>>>>>>>
>>>>>>>cap arrays are more art than science right now. I wish I had hard
>>>>>>>
>>>>
>>>>data
>>>>
>>>>>>>
>>>>>>>showing how good arrays as a function of X, Y, Z compared to
>>>>>>>
>>>>
>>>>discretes,
>>>>
>>>>>>>
>>>>>>>but I don't have the time or resources to do this personally.
>>>>>>>
>>>>>>>I'd sure be interested in hearing if anybody else has tried this
>>>>>>>
>>
>>or
>>
>>>>
>>>>has
>>>>
>>>>>>>
>>>>>>>hard data.
>>>>>>>
>>>>>>>-Jerry
>>>>>>>
>>>>>>>-----Original Message-----
>>>>>>>From: <mailto:si-list-bounce@xxxxxxxxxxxxx>si-list-bounce@xxxxxxxxxxxxx
>>>>>>>
>>>>
>>>>[mailto:si-list-bounce@xxxxxxxxxxxxx]
>>>>
>>>>>>>
>>>>>>>On Behalf Of SI List
>>>>>>>Sent: Tuesday, December 30, 2003 5:21 AM
>>>>>>>To: <mailto:si-list@xxxxxxxxxxxxx>si-list@xxxxxxxxxxxxx
>>>>>>>Subject: [SI-LIST] Bypass Capacitor Selection
>>>>>>>
>>>>>>>Dear All,
>>>>>>>
>>>>>>>After studying many books, the bottom line for high frequency
>>>>>>>
>>
>>bypass
>>
>>>>>>>
>>>>>>>capacitor selection seems to be the following:
>>>>>>>
>>>>>>>Use the smallest possible package and then take the largest valued
>>>>>>>capacitor available in that package.
>>>>>>>
>>>>>>>Although 0201 capacitors are available, they are kind of hard to
>>>>>>>assemble. So in our design, we are thinking of using 0402 X5R
>>>>>>>
>>
>>parts.
>>
>>>>>>>
>>>>>>>In a 0402 package, the largest value available seems to be 1 uF.
>>>>>>>
>>>>>>>My frequency range of interest is DC to 500 MHz. In addition to
>>>>>>>
>>
>>the
>>
>>>>>>>
>>>>>>>bypass capacitors, I know that there must be a pair of closely
>>>>>>>
>>
>>spaced
>>
>>>>>>>
>>>>>>>VCC/GND reference planes.
>>>>>>>
>>>>>>>My questions:
>>>>>>>1. Does it make sense to only use 1 uF 0402 capacitors for
>>>>>>>
>>
>>bypassing?
>>
>>>>>>>
>>>>>>>Other people often use a combination of 1 nF/10nF/100nF. 2. I have
>>>>>>>
>>>>
>>>>been
>>>>
>>>>>>>
>>>>>>>looking at the frequency characteristic of 100 nF 0402 X5R
>>>>>>>
>>
>>capacitors
>>
>>>>>>>
>>>>>>>given in the data sheets of different manufacturers. The
>>>>>>>
>>
>>impedance vs.
>>
>>>>>>>
>>>>>>>frequency plot often looks quite different from manufacturer to
>>>>>>>manufacturer. Should I choose the manufacturer with the best
>>>>>>>
>>
>>frequency
>>
>>>>>>>
>>>>>>>characteristic or are all such parts almost equivalent? 3. Does it
>>>>>>>
>>>>
>>>>make
>>>>
>>>>>>>
>>>>>>>sense to use surface mount capacitor arrays for bypassing?
>>>>>>>
>>>>>>>Thanks for all your expert feedback.
>>>>>>>
>>>>>>>Best regards,
>>>>>>> Martin Heimlicher, heimlicher__at__enclustra//dot//com
>>>>>>>
>>>>>>>------------------------------------------------------------------
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>> <http://www.qsl.net/wb6tpu>http://www.qsl.net/wb6tpu
>>
>>
>>
>>
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