[SI-LIST] Re: Backplane speed
- From: "Tom Biggs" <tbiggs@xxxxxxxxxxxxxxxxxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 26 Apr 2007 09:57:35 -0700
=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Kihong Kim
Sent: Thursday, April 26, 2007 8:53 AM
To: si-list
Subject: [SI-LIST] Backplane speed
Dear SI professionals,
Could anyone give some inputs for *backplane interconncetion* (chip on
blade-to-backplane-to-chip on blade)?
I want to hear especially your opinion to start the project I am engaged
in right now.
1. What is the state of the art technolgy for backplane interconnection?
Accelerant used to have a multilevel, auto-equalizing SerDes, but they
got swallowed up by Synopsys and don't offer this anymore.
Similar advanced features can be found in Rambus's cores:
http://www.rambus.com/us/products/advanced_backplane/
2. Are signal impairment compensation technolgy, such as Pre-emphasis,
equalizer etc, are practically well applied in real design world? Or is
it just a sales pitch? (3G, 6G, 10G, 40G,..)
3G has been working for years using these technologies. 6G is shipping
from several manufacturers.
3. I know some designers suppress these features and stick to classical
external termination method because of, FOR EXAMPLE, the issues like
SSN, power consumption etc. Do you have Other issues?
External termination is rare in the designs I've seen.=20
4. For technolgy I see the issues for latency (few hundreds nanosec for
FEC..) and power consumption (total bay power constraints...). Any
opinion on this?
Look at the datasheets of the various SerDes manufacturers. Check out
the XAUI and PCI express and other SerDes specs (for example: you won't
find FEC). You'll find your answers.
5. Would temperature mean to SI for high-speed backplane? If it does,
what sensitity?
Temperature affects ICs. If you have Spice models you can model the
temperature affects.
6. Want to discuss for today's and two years after technolgy, in terms
of speed (bit/sec) associated to the specific technolgy (mostly serial
IO technolgy, I presume).
Ask the IC and IP reps for their roadmaps.
I am having trouble to get these kind of infos because most vendors are
so conservative for their IP issues.
Best Regards,
Kihong Joshua Kim
SI Consultant, Photonics and Electronics
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