[SI-LIST] Re: Backplane speed
- From: "Kihong Kim" <joshuakh@xxxxxxxxx>
- To: tbiggs@xxxxxxxxxxxxxxxxxxxxx
- Date: Fri, 27 Apr 2007 08:42:31 -0400
Thanks for your inputs and Tom's.
Let's focus more one at a time. Regarding FEC (Question # 4),
I have seen FEC in 10GBASE-KR (a kind of backplane std) discussion. You
might find one material if you link to
http://www.ieee802.org/802_tutorials/july06/10GBASE-KR_FEC_Tutorial_1407.pdf
Problem I have is I haven't follow up the discussion so I don't know the
detail
Is there anyone who could give me some more background on this?
For 3G backplane, do they (system companies) fully utilize
the preemphasis/equalizer today without ANY issues?
For example, 10^-12 BER requirement in terms of Jitter, Attenuation( S11 in
conjunction with SNR), SSN(how many channels with good scalability will
be practically fired from one blade to the fabric card through backplane)
and power consumption in case increased number of interconnections due to
its Automatic Gear (it is kind of starightforward to guess most automatic
controller , in this case adaptible/or fixed signal compensation means,
consumes much more power consumption than Classical ones).
These are the questions in my mind to solve Gedanken experiment for my
customer (more for question #4).
Any inputs/feedback/your advice will be pretty much appreciated.
Regards,
Kihong Joshua Kim
SI Consultant in Photonics and Electronics
On 4/26/07, Tom Biggs <tbiggs@xxxxxxxxxxxxxxxxxxxxx> wrote:
>
> =20
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Kihong Kim
> Sent: Thursday, April 26, 2007 8:53 AM
> To: si-list
> Subject: [SI-LIST] Backplane speed
>
> Dear SI professionals,
> Could anyone give some inputs for *backplane interconncetion* (chip on
> blade-to-backplane-to-chip on blade)?
> I want to hear especially your opinion to start the project I am engaged
> in right now.
>
> 1. What is the state of the art technolgy for backplane interconnection?
>
> Accelerant used to have a multilevel, auto-equalizing SerDes, but they
> got swallowed up by Synopsys and don't offer this anymore.
> Similar advanced features can be found in Rambus's cores:
> http://www.rambus.com/us/products/advanced_backplane/
>
> 2. Are signal impairment compensation technolgy, such as Pre-emphasis,
> equalizer etc, are practically well applied in real design world? Or is
> it just a sales pitch? (3G, 6G, 10G, 40G,..)
>
> 3G has been working for years using these technologies. 6G is shipping
> from several manufacturers.
>
> 3. I know some designers suppress these features and stick to classical
> external termination method because of, FOR EXAMPLE, the issues like
> SSN, power consumption etc. Do you have Other issues?
>
> External termination is rare in the designs I've seen.=20
>
> 4. For technolgy I see the issues for latency (few hundreds nanosec for
> FEC..) and power consumption (total bay power constraints...). Any
> opinion on this?
>
> Look at the datasheets of the various SerDes manufacturers. Check out
> the XAUI and PCI express and other SerDes specs (for example: you won't
> find FEC). You'll find your answers.
>
> 5. Would temperature mean to SI for high-speed backplane? If it does,
> what sensitity?
>
> Temperature affects ICs. If you have Spice models you can model the
> temperature affects.
>
> 6. Want to discuss for today's and two years after technolgy, in terms
> of speed (bit/sec) associated to the specific technolgy (mostly serial
> IO technolgy, I presume).
>
> Ask the IC and IP reps for their roadmaps.
>
> I am having trouble to get these kind of infos because most vendors are
> so conservative for their IP issues.
>
> Best Regards,
>
> Kihong Joshua Kim
> SI Consultant, Photonics and Electronics
>
>
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